Low power CMOS latch

Details Low power CMOS latch Low power CMOS latch

1996-03-12

1998-06-02

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327212, 327203, H03K 3356

Patent

active

057606277

ABSTRACT:
A latch comprises first and second NFETs and a first inverter. Data is applied without inversion to the gate of the first NFET and via the first inverter to the gate of the second NFET. A third NFET has a drain connected to the sources of the first and second NFETs. A clock is applied to the gate of the third NFET. Thus, there is only one NFET subject to the constant switching the clock, and therefore the constant power dissipation caused by the clock. To latch the data from the first and second NFETS, first and second inverters are connected in paralle with each other such that the output of each inverter is connected to the input of the other inverter. The input of one of the inverters is connected to the drain of the first NFET and the input of the other inverter is connected to the drain of the second NFET. A second stage of latching is also disclosed.

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