Low-power CMOS flip-flop

Details Low-power CMOS flip-flop Low-power CMOS flip-flop

2003-04-03

2004-08-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S210000, C327S218000

Reexamination Certificate

active

06777992

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a flip-flop for a computing device, and more particularly, the present invention relates to a flip-flop for a computing device that utilizes energy recovery to reduce power consumption.
BACKGROUND OF THE INVENTION
Conventional computing systems utilize a plurality of flip-flops in conjunction with a clock signal generating circuit. The flip-flops store binary states, such as 1's and 0's contingent on the absence or presence of a voltage or charge in the flip-flop. The binary states, read or written in the flip-flops, are then used for combinational boolean logic for operation and calculation procedures in the computing system. When writing a logic state in the flip flop by a device external to the flip flop is desired, an oscillating voltage or clock signal operates the flip fop to cause a voltage value representative of the stored state to be stored to be written to the latching circuit in the flip-flop, latch the voltage value and hold it available for reading devices external to the flip-flop. The clock signal is commonly a square wave that drives a gate of a transistor of the flip-flop. A clock signal generating circuit, external to the flip-flops, generates the signal to effectuate read, write and timing processes in the computing device. The square or abrupt signal drives the gates of transistors in the flip-flop to turn them on and off in a relatively quick manner.
While this structure effectively allows a computing system to effectuate reading of stored logic states contained within the flip-flops, drawback exists. Specifically, only a portion of a computing system's flip-flops are actually read during any given read request. The remainder, however, still receive the clock signal. Commonly, the energy of the clock signal driving the unread flip-flops is dissipated therein, thereby creating energy inefficiencies and increased heat dissipation. When this dissipation effect is multiplied with the numerous flip-flops contained within a computing device, the overall efficiency of that computing device is compromised. The present invention was developed in light of these and other drawbacks.
SUMMARY OF THE INVENTION
A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.
Other aspects of the invention will be apparent to those skilled in the art after reviewing the drawings and the detailed description below.


REFERENCES:
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5036217 (1991-07-01), Rollins et al.
patent: 5146109 (1992-09-01), Martignoni et al.
patent: 5311071 (1994-05-01), Ueda
patent: 5384493 (1995-01-01), Furuki
patent: 5473526 (1995-12-01), Svensson et al.
patent: 5506520 (1996-04-01), Frank et al.
patent: 5517145 (1996-05-01), Frank
patent: 5526319 (1996-06-01), Dennard et al.
patent: 5559478 (1996-09-01), Athas et al.
patent: 5587676 (1996-12-01), Chowdhury
patent: 5734285 (1998-03-01), Harvey
patent: 5838203 (1998-11-01), Stamoulis et al.
patent: 6037816 (2000-03-01), Yamauchi
patent: 6069495 (2000-05-01), Ciccone et al.
patent: 6278308 (2001-08-01), Partovi et al.
patent: RE37552 (2002-02-01), Svensson et al.
patent: 6563362 (2003-05-01), Lambert
patent: 6608512 (2003-08-01), Ta et al.
Low-Power Digital Systems Based on Adiabatic-Switching Principles by William C. Athas, Lars “J.” Svensson, Member IEEE, Jeffrey G. Koller, Nestoras Tzartzanis, and Eric Ying-Chin Chou, Student Member, IEEE in the IEEE Transaction On Very Large Scale Integration (VLSI) Systems, vol. 2, No. 4, Dec. 1994.
A Resonant Clock Generator for Single-Phase Adiabatic Systems by Conrad H. Ziesler, Suhwan Kim and Marios C. Papaefthymiou. P)ublished ISLPED '01, Aug. 6-7, 2001.
Energy Recovering Static Memory by Joohee Kim, Conrad H. Ziesler & Marios C. Papaefthymiou. Published ISLPED '02, Aug. 12-14, 2002.
PCT International Search Report dated Sep. 29, 2003—PCT/US03/10320.

Affiliated with

Also associated with

Rating

Low-power CMOS flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-power CMOS flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-power CMOS flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3353396