Static information storage and retrieval – Floating gate – Particular connection
Patent
1995-06-06
1998-05-19
Yoo, Do Hyun
Static information storage and retrieval
Floating gate
Particular connection
36518526, 36518529, 36518909, G11C 1602
Patent
active
057544719
ABSTRACT:
A low power CMOS array cell for use in a PLD device is disclosed. The cell utilizes controlled avalanche injection at the p-n junction of a transistor in the CMOS cell for programming and erasing, resulting in lower voltages than with Fowler-Nordheim tunneling and lower currents than channel hot carrier injection during program and erase. A depletion transistor having a gate connected to its source has a source-drain path supplying current to the CMOS cell to limit current required during avalanche injection.
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Lin Jonathan
Peng Jack Zezhong
Advanced Micro Devices , Inc.
Yoo Do Hyun
LandOfFree
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