Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-01-12
1993-03-23
Westin, Edward P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307452, 307481, H03K 1716, H03K 1920
Patent
active
051967430
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
The present invention relates to the field of switching low power electronic circuits and particularly CMOS logic circuits. More particularly, the present invention relates to reducing or minimising the current drawn by a switchable electronic circuit at any point in time, such as CMOS circuitry.
BACKGROUND
The basic CMOS logic gate, as its known to those skilled in the art, consumes essentially no or a relatively small amount of power, except when it is actually in a switching state (a change in input causes the output to change). Circuits including CMOS logic gates often comprise a large number of such gates, synchronised to a single clock signal. Synchronous systems are preferred from a design standpoint, and their synchronous behaviour is believed to be well understood by people skilled in the art. All logic gates of such a circuit switch simultaneously, and the load presented to the power source appears as a short, heavy burst, synchronised with the clock. Compensation for this heavy power drain, as a result of current flowing simultaneously into these gates, often necessitates the use of a large supply reservoir capacitor in the power source. This large capacitor is often undesirable.
OBJECTS OF INVENTION
An object of the present invention is to provide a method and/or device wherein the current drawn by a circuit is distributed over a predetermined period of time.
A further object of the present invention is to provide a device and/or method which has a reduced dependence on a charge storage reservoir when switching a circuit comprising a relatively large number of CMOS gates.
SUMMARY OF INVENTION
The present invention provides a method of switching a circuit comprising a plurality of non or minimal power consumption logic elements, said circuit comprising at least a first switchable logic element and a second switchable logic element, the method comprising the steps of:
enabling said first logic element so as to allow said first logic element to reach a steady logic state, enabling said second logic element so as to allow said second logic element to reach a steady logic state, wherein:
enabling of said second element is not commenced until said first element reaches a substantially steady logic state.
The present invention also provides a device for switching a circuit comprising a plurality of non or minimal power consumption logic elements, said circuit comprising at least a first switchable element and a second switchable element, said device comprising:
a timing means coupled to said first element and being adapted to enable said first element so as to allow said first element to reach a steady logic state, said timing means further being coupled to said second element and being adapted to enable said second element so as to allow said second element to reach a steady logic state, wherein said timing means enables the second element after the first element reaches a substantially steady logic state.
The present invention also provides a method and device as described above, wherein the enabling of each element is co-ordinated with successive cycles of an AC power source.
The present invention also provides a method and device as described above, wherein high switching currents are drawn directly form an AC power source.
The present invention also provides a method and device as described above, wherein enabling of each circuit or part thereof is provided in a staggered relationship.
The present invention also provides a method and device as described above, wherein, within each element, gates or groups of gates are further selectively enabled in a staggered relationship.
The above methods or device(s) may be included in a clocking circuit. The timing means of the device may also incorporate delay elements to enhance device timing.
The present invention may be applicable to I.C. circuits, or other low current drawing circuit, including passive transponders.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic view of a 2-phase clocking circuit according to the inven
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Magellan Corporation (Australia) Pty. Ltd.
Sanders Andrew
Westin Edward P.
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