Low power clocked set/reset fast dynamic latch

Details Low power clocked set/reset fast dynamic latch Low power clocked set/reset fast dynamic latch

1996-06-21

1997-07-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, 327217, H03K 3356

Patent

active

056465661

ABSTRACT:
A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.

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