Low power clock generator circuit

Details Low power clock generator circuit Low power clock generator circuit

1981-12-24

1985-08-13

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Including ring counter

307453, 307481, 307482, 377 47, 377117, 377126, H03K 2322

Patent

active

045354650

ABSTRACT:
A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.

REFERENCES:
patent: 3518451 (1970-06-01), Booher
patent: 4164666 (1979-08-01), Hirasawa
patent: 4165541 (1979-08-01), Varshney et al.
patent: 4316106 (1982-02-01), Young et al.

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