Low power clock generator

Details Low power clock generator Low power clock generator

1985-04-30

1987-10-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307578, 307200B, 307443, H03K 513, H03K 1901, H03K 19003, H03K 17687

Patent

active

047016337

ABSTRACT:
A clock delay circuit of the type used in semiconductor dynamic read/write memory device employs pull-up and pull-down output transistors connected in series between a voltage supply and ground. Excess current in this series path is minimized by a circuit holding the gate of the output pull-up transistor to a low voltage until the gate of the pull-down transistor goes low. Then, the gate of the pull-up transistor is booted above the supply voltage. Also, tendency for the output voltage to rise above ground during the delay period is avoided.

REFERENCES:
patent: 4081701 (1978-03-01), White, Jr. et al.
patent: 4239991 (1980-12-01), Hong et al.
patent: 4239993 (1980-12-01), McAlexander et al.
patent: 4508978 (1985-04-01), Reddy
patent: 4521701 (1985-06-01), Reddy
patent: 4570088 (1986-02-01), Nozaki et al.

Affiliated with

Also associated with

Rating

Low power clock generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power clock generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power clock generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1614087