Low-power clock gating circuit

Details Low-power clock gating circuit Low-power clock gating circuit

2007-11-27

2009-08-18

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S212000, C327S218000

Reexamination Certificate

active

07576582

ABSTRACT:
Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

REFERENCES:
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6844767 (2005-01-01), Shelor
patent: 7023240 (2006-04-01), Elappuparackal
patent: 100294695 (2001-04-01), None
patent: 1020040040732 (2004-05-01), None

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