Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2001-08-06
2003-03-18
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S379000, C327S538000, C327S545000, C326S033000
Reexamination Certificate
active
06535039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an adjusted circuit a slew rate (an amount of change in output voltage per unit time for step input) of whose output is dependent on a bias current and a circuit automatically adjusting the value of the bias current to achieve low power with proper slew rate.
2. Description of the Related Art
FIG. 9
is an illustration of bias adjustment to a prior art semiconductor integrated circuit
10
X including an adjusted circuit
11
whose slew rate is dependent on a bias current IB.
To the adjusted circuit
11
, the bias current IB is provided from a bias circuit
12
. The output of the adjusted circuit
11
is connected to another circuit not shown or an output terminal of the semiconductor integrated circuit
10
X and a load impedance measured at the output of the adjusted circuit
11
is Z
L
.
FIG. 10
shows a sample and hold circuit as an adjusted circuit
11
of
FIG. 9
, which is a combination of a switched capacitor circuit and an operational amplifier
13
X.
FIG. 10
shows a case where the load impedance can be approximated by a capacitance CL.
FIG. 11
are waveform diagrams showing operation of the circuit of FIG.
10
.
The switches of
FIG. 10
are controlled by two phase clocks &phgr;
1
and &phgr;
2
shown in
FIG. 11
, wherein a high and a low of each clock correspond to ON and OFF of switches controlled by the clock. The switches P
11
, P
12
and P
13
are is controlled by the clock &phgr;
1
and switches P
21
and P
22
are controlled by the clock &phgr;
2
.
The input and output voltages of the adjusted circuit
11
are denoted by Vi and Vo, respectively. When the clock &phgr;
1
is high, the both ends of a integrating capacitor C
2
are grounded to be reset and a sampling capacitor C
1
is simultaneously charged with the input voltage Vi. The electric charge Q
1
charged on the sampling capacitor C
1
is C
1
×Vi. Then, when the clock &phgr;
2
goes high, the electric charge Q
1
is transferred to the integrating capacitor C
2
and if a sufficient settling time is given, the electric charge Q
2
of the integrating capacitor C
2
becomes C
2
×Vo. Since Q
1
=Q
2
, a relation Vo=(C
1
/C
2
)Vi holds.
When the adjusted circuit
11
is operated with a high speed clock signal, unless the adjusted circuit
11
has a sufficient drive ability for the load capacitance CL, the slew rate is insufficient and Vo<(C
1
/C
2
)Vi, whereby a necessary output amplitude will not be obtained.
In design, the bias current IB to be provided to the operational amplifier
13
X is determined such that a necessary slew rate can be obtained under the worst conditions of a power supply voltage, temperature and a deviation in circuit element characteristics occurring in fabrication process. Besides, there are taken into consideration a variation in drive ability of the operational amplifier
13
X in company with a variation in the bias current IB and a variation in the capacitance CL.
In ordinary case, however, the worst conditions does not occur, thereby resulting in excessive power consumption.
FIG. 12
shows the output voltages Vo, with respect to time between t
1
and t
3
of
FIG. 11
, of adjusted circuits
11
under different conditions fabricated on the basis of the same design. In
FIG. 12
, VLL denotes the lowest limit value of a necessary output voltage Vo for ensuring a normal operation of the adjusted circuits
11
under the worst conditions.
Referring back to
FIG. 9
, in order to solve the problem of excessive power consumption, a configuration was adopted in the prior art in which a bias circuit
12
capable of adjusting the bias current IB is incorporated in the semiconductor integrated circuit
10
X, a bias current IB having the same value as the bias current IB provided to the adjusted circuit
11
is taken out from the bias circuit
12
to the outside and measured with an ammeter
14
, and such a trimming adjustment is performed that the bias current IB is adjusted by an adjustment circuit
15
X to make the bias current IB within a given range. This adjustment is performed in the final stage of a fabrication process of the semiconductor integrated circuit
10
X.
However, since characteristic variations in load impedance and a variation in load impedance caused by variations in power supply voltage and temperature are not taken into consideration, the bias current BI has to be determined assuming that the load impedance has the maximum value, leading to insufficient reduction in power consumption. Further, since adjustment operation for the bias current IB is necessary in fabrication process of the semiconductor integrated circuit
10
X, the cost increases.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit capable of achieving more of power consumption of a circuit, whose slew rate is dependent on a bias current, without adjusting the bias current thereof prior to product shipment.
In one aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a replica circuit of an adjusted circuit whose slew rate is dependent on a bias current; and a bias current automatic adjustment circuit; wherein the replica circuit is repeatedly operated for adjustment. This automatic adjustment circuit comprises: an evaluation circuit; a comparator circuit; and a bias adjustment circuit.
In the evaluation circuit, processing is repeated, wherein the processing includes: resetting an output thereof; obtaining a difference between first and second values of an output of the replica circuit given times, the first and second value being respective ones at respective times when first and second time intervals has elapsed after a given value having been step-inputted to the replica circuit; and successively summing the differences. In the comparator circuit, a value obtained by the successively summing is compared with a reference value. The bias adjustment circuit changes the bias currents of the replica circuit and the adjusted circuit according to a comparison result of the comparator circuit at every given times.
According to this semiconductor integrated circuit, since even if there are variations in bias current and output load of adjusted circuit due to variations in fabrication process, power supply and environmental temperature, the bias current is automatically and properly adjusted coping with the variations, and low power consumption can be realized. Further, a parasitic capacitance of circuit elements of the automatic adjustment circuit exerts no adverse influence on a main signal system including the adjusted circuit, and in addition automatic adjustment of the bias current of the adjusted circuit can be performed without ceasing operation of the main signal system in parallel thereto. Still further, there is no need to perform bias current adjustment operation at the final stage of fabrication of the semiconductor integrated circuit, thereby enabling reduction in cost thereof.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
REFERENCES:
patent: 5107224 (1992-04-01), Meyer
patent: 5831562 (1998-11-01), Van Auken et al.
patent: 6154083 (2000-11-01), Gaudet et al.
patent: WO 01/43277 (2001-06-01), None
Ikeshita Makoto
Mizutani Tohru
Nanba Hiromi
Takeyabu Masato
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lam Tuan T.
Nguyen Minh
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