Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2001-08-20
2003-08-19
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S203000, C365S204000
Reexamination Certificate
active
06608771
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor circuit design, and more particularly towards circuit structures for low power operation of content addressable memories and random access memories.
2. Description of Prior Art
Content addressable memory (CAM) circuit structures are typically used to allow fast and efficient searches, translations, or pattern matching of memory content. CAM provides a general solution to memory searches; unlike standard memories that associate data with an address, a CAM associates an address with data. When data is presented on the inputs of the CAM, the CAM searches for a match for the data in the CAM without regard to address. When a match is found the CAM identifies the address location of the data. In microprocessors, CAMs have been used most notably for tag matching in Translation Lookaside Buffers (TLBs) and associative caches, and to resolve instruction dependencies in rename and issue pipeline stages.
One problem associated with CAMs is power consumption. For example, in a CAM implemented as a dynamic wired XNOR function, where all match transistors are connected to one matchline, the matchline is precharged to a high logic value before evaluating the function. Whenever a mismatch occurs, the matchline is discharged. In situations where mismatches are prevalent, the frequent recharging of the matchline consumes considerable power. This high power consumption limits the physical size of CAMs and also limits its use in low power applications.
Recent work has proposed cascaded matching logic, where the match transistors are connected in serial to form an AND function rather than a wired XNOR function. This scheme prevents the matchline from being discharged every cycle when a mismatch occurs, thereby reducing power consumption. In order to provide high speed matching, a sense-amp can be added to the output. Alternatively, the AND function is decomposed into several sub-functions. While these methods reduce power consumption by reducing the frequency of precharging the matchline node, both of these approaches introduce additional sources of power consumption by introducing short circuit currents (sense-amp in its linear region) and/or internal nodes (decomposed AND function) that need to be charged and discharged. An AND function also introduces additional gate capacitance as extra transistors (static logic) and/or larger transistors (high stack domino logic) are introduced.
The main problem with the AND function approach however is that it is not as scalable as the wired XNOR approach. In an AND function the transistor stack height is dependent on the number of tag-bits that are to be matched. The delay of the logic (R*C) increases quadratically with stack height as capacitance (C) and resistance (R) is added for each additional transistor. In a wired XNOR function, the delay increase is linear with number of tag-bits, as only capacitance (but not resistance) is added to the critical path.
Referring to power consumption in dynamic wired XNOR match logic, one problem is the logic that interfaces to the match result. If the match result is connected to static logic, then intermediate nodes in the logic function may also be charged and discharged each cycle due to the precharging and discharging of the matchline node, unnecessarily wasting power. If dynamic logic is used, then it needs to be triggered by an evaluation signal rather than by the data signals (match results) themselves. This “sampling” of the data signals introduces extra delay overhead as safety margins need to be used to ensure that the domino logic is not evaluated before all data signals have reached their final value. Sampling also introduces additional power dissipation as the extra gate capacitance of the evaluation transistor of the domino logic needs to be driven each cycle. Referring to interfacing with logic dependent on the match result, the main problem with the dynamic wired XNOR match logic is that it generates an event on the matchline when there is not a match, rather than when there is a match.
Accordingly, it would be desirable to add the low power advantages of the AND function approach to the speed advantages of the dynamic wired XNOR function. Circuit structures that can combine these two features are presented in this text.
Random Access Memory (RAM) circuit structures are mainly used to efficiently store and read data. However, RAM structures generally have high power consumption due to precharging and discharging of high capacitance bitlines every cycle a read takes place. In addition, when sense-amps are used, two bitlines, data and data′, are needed, further increasing power consumption. Fast sense-amps also consume significant power as the sense transistors are put in their linear region in order to react quickly to a voltage drop on one of the bitlines, creating short-circuit current. If sense-amps are not used, the read operation may be significantly slowed due to the time it takes for the size limited read and storage transistors to discharge the bitline. This text presents an alternative fast low power solution to this problem by reducing the capacitance on the bitlines through banking.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method is provided for matching two data sources through a wired exclusive-nor (XNOR). The method includes discharging a first tag line and a second tag line associated with a first tag bit, and precharging a matchline, connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices. The method includes reading a plurality of tag bits, including the first tag bit and corresponding data bits, onto a plurality of corresponding tag lines and data lines respectively, and determining a match between each tag bit and data bit, wherein the matchline is pulled to a second potential upon each match logic device indicating a match, and wherein the matchline being held at the first potential upon any match logic device indicating a mismatch.
Each match logic device has a pulling strength, wherein the pulling strengths are ratioed, the match logic devices pulling to the first potential being stronger than the match logic devices pulling to the second potential, wherein upon the match logic devices simultaneously pulling to different potentials, the matchline is clamped at the first potential.
The method further.comprises pulsing a tag line by resetting the tag line to a logic 0 after the match logic devices have evaluated whether the corresponding tag bit has a logic value of 1. Pulsing a tag line further comprises latching a tag bit, and resetting a latch to a value of logic 0 upon determining the tag bit to be a value of logic 1 after the match logic devices have evaluated whether the corresponding tag bit has a logic value of 1. The method includes pulling the matchline partially towards the second potential upon determining a match for each tag bit, and pulling the matchline to the second potential using a sense-amplifier.
The XNOR function is a static wired XNOR function, and the method further comprises pulling, with at least one tag match function, the matchline to the second potential upon evaluating a match, and pulling, with at least one tag match function, the matchline to the first potential upon evaluating a mismatch, wherein the matchline implements a static wired XNOR function.
The wired XNOR function is implemented as a dynamic XNOR-AND function, and the method includes pulling, with a set of tag match functions, to the first potential, and pulling, through an AND structure of tag match functions, to the second potential, wherein one or more tag match functions are connected to one another in series forming an AND(XNOR(tag[i]), . . . ,XNOR(tag[i+j])) function, where i and j indicate the corresponding tag bits of the tag match functions.
The first potential is ground and the second potential is VDD. Alternatively, the firs
Cook Peter W.
Jacobson Hans M.
Kudva Prabhakar N.
Schuster Stanley Everett
Elms Richard
Hur Jung H.
International Business Machines - Corporation
Wallace Nathaniel I.
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