Low power capacitive load driving circuit

Details Low power capacitive load driving circuit Low power capacitive load driving circuit

1995-07-28

1998-03-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327284, 377 63, H03K 1716, G11C 2704

Patent

active

057317224

ABSTRACT:
A circuit for driving a capacitive load uses a plurality of driving signals with different phases including a quiescent time, and a driving time having a driving duration and an other time. An inductance element is connected across the driving terminals of the capacitive load, and a switch circuit is provided between a driving voltage source and the capacitive load. During the quiescent time, the switch circuit is closed to make the driving voltages the same potential, minimizing energy loss since no current flows during the quiescent time. During the driving time, the switch circuit is closed for a predetermined driving duration to clamp a sine wave around the peaks of the waveform, and the switch circuit is open during the other time when the sine wave is not at any of its peaks.

REFERENCES:
patent: 3858059 (1974-12-01), Khanna
patent: 4597092 (1986-06-01), Furusawa et al.
patent: 4877980 (1989-10-01), Kubinec
patent: 5285370 (1994-02-01), Axer et al.
Patent Abstracts of Japan; vol. 014 No. 139 (E-0903), 15 Mar. 1990 & JP-A-02 002290 (Toshiba Corp) 8 Jan. 1990.
Patent Abstracts of Japan; vol. 014 No. 099 (E-0893), 22 Feb. 1990 & JP-A-01 303757 (Hitachi Ltd) 7 Dec. 1989.
Patent Abstracts of Japan; vol. 005 No. 150 (P-081), 22 Sep. 1981 & JP-A-56 080893 (Matsushita Electric Ind Co Ltd) 2 Jul. 1981.

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