Low-power Booth-encoded array multiplier

Details Low-power Booth-encoded array multiplier Low-power Booth-encoded array multiplier

2007-05-29

2007-05-29

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10268602

ABSTRACT:
An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

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