Low power bipolar transistors with low parasitic losses

Details Low power bipolar transistors with low parasitic losses Low power bipolar transistors with low parasitic losses

2008-05-13

2008-05-13

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S197000, C257S565000

Reexamination Certificate

active

07372084

ABSTRACT:
Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

REFERENCES:
patent: 5506427 (1996-04-01), Imai
patent: 6320211 (2001-11-01), Morishita
patent: 6911716 (2005-06-01), Chen et al.
patent: 2002/0089038 (2002-07-01), Ning
patent: 2003/0166325 (2003-09-01), Chow et al.
patent: 2004/0046182 (2004-03-01), Chen et al.

Affiliated with

Also associated with

Rating

Low power bipolar transistors with low parasitic losses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power bipolar transistors with low parasitic losses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power bipolar transistors with low parasitic losses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2813623