Low power BICMOS memory using address transition detection and a

Static information storage and retrieval – Addressing – Sync/clocking

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36518905, 365233, 36523006, G11C 700

Patent

active

052335658

ABSTRACT:
A BICMOS memory performs address transition detection on each address signal. A first ECL difference amplifier detects a low-to-high transition with a first input being the address signal, and a second input being the address signal delayed and level-shifted. A second ECL difference amplifier uses a complement of the first and second inputs to detect a high-to-low transition. The outputs of two corresponding ECL difference amplifiers for each address signal are wire-ORed together to form the address transition detection signal, which is delayed for first, second, and third predetermined times to sequentially perform row predecoding, row decoding, and block decoding, respectively. The decoding is performed by logic circuits using modified Widlar current sources, which decrease the current required except during decoding, as indicated by a corresponding address transition detection signal. The saving in current allows faster ECL circuits to be used and decreases peak current on internal power supply lines.

REFERENCES:
patent: 4965474 (1990-10-01), Childers et al.
patent: 4991140 (1991-02-01), Wang et al.
Takada et al., "5ns 1MB ECL BICMOS SRAM", ISSCC Digest of Technical Papers, 1990, p. 138.

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