Low-power battery backup circuit for semiconductor memory

Details Low-power battery backup circuit for semiconductor memory Low-power battery backup circuit for semiconductor memory

1980-02-06

1981-09-08

Hecker, Stuart N.

Static information storage and retrieval

Powering

Data preservation

307 64, G11C 700

Patent

active

042888654

ABSTRACT:
A battery backup circuit for an MOS memory which has a multiplexed pin (WE) that functions to provide backup power to a memory cell array (50) upon loss of primary power V.sub.cc. A voltage comparator (10) detects when the primary power V.sub.cc becomes less than the backup voltage on the WE terminal. Upon detection of loss of primary power the memory cell array (50) is powered by a connection to the WE terminal. A primary power status signal (POK) indicates the status of the primary power and is driven to a state indicating insufficient circuit voltage for normal operation when V.sub.cc drops below an acceptable limit or when there is inadequate substrate bias. The circuit of the present invention further generates an inhibit signal to prevent the operation of peripheral circuits (70) to write data into the memory cell array (50) upon detection of a failure of primary power. The inhibit signal is generated when primary power is lost or when the substrate bias is inadequate. A low-power auxiliary pump generator (92) provides a sufficient substrate bias to maintain the data pattern in the memory cell array (50) during the backup mode.

REFERENCES:
patent: 3859638 (1975-01-01), Hume
patent: 4122359 (1978-10-01), Breikss
patent: 4148099 (1979-04-01), Lauffer et al.

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