Low power asynchronous latch

Details Low power asynchronous latch Low power asynchronous latch

1976-02-18

1977-03-01

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307251, 307270, H03K 3286, H03K 3353, H03K 1704, H03K 1710

Patent

active

040103889

ABSTRACT:
The output of a fast-acting ratioless logic circuit is monitored by a sensing device, and when one selected logic output is sensed, a voltage is applied to the output node to latch the output to that state. To effect rapid return to the other state, a switch is provided to deactivate the applied voltage when the output node is established at the other state. The latching is made permanent by the further application of a refresh clock which periodically pulses the output node whenever the one selected state is latched.

REFERENCES:
patent: 3562559 (1971-02-01), Rapp
patent: 3639813 (1972-02-01), Kamoshida et al.
patent: 3755690 (1973-08-01), Smith
patent: 3812384 (1974-05-01), Skorup
patent: 3846643 (1974-11-01), Chu et al.
patent: 3911289 (1975-10-01), Takemoto
patent: 3942047 (1976-03-01), Buchanan
De Simone, "Dynamic Gating Circuit," IBM Tech. Discl. Bull., vol. 18, No. 3, pp. 638-639, Aug. 1975.

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