Low-power asynchronous counter and method

Details Low-power asynchronous counter and method Low-power asynchronous counter and method

2011-01-04

2011-01-04

Cox, Cassandra (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

Using bistable regenerative trigger circuits

C377S037000

Reexamination Certificate

active

07864915

ABSTRACT:
Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).

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International Search Report and Written Opinion—PCT/US09/060063, International Searching Authority—European Patent Office, Dec. 23, 2009.

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