Low power, area-efficient circuit to provide clock...

Details Low power, area-efficient circuit to provide clock... Low power, area-efficient circuit to provide clock...

2003-08-05

2004-12-07

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

C327S407000

Reexamination Certificate

active

06828830

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to electronic systems and circuits therefor, and is particularly directed to a clock generator circuit for controllably asserting either an internal or an external clock for chip circuitry synchronization.
BACKGROUND OF THE INVENTION
Many integrated circuits, such as, but not limited to power management pulse width modulators, employ an internal clock generator. In some applications it is desirable to override the internally generated clock with an external clock to provide synchronization with other electronics in the system. It is desirable to do this without having to add a ““clock selected” or control” pin to select an internal vs. an external clock, i.e., it is desirable to “sense” the presence of an external clock signal, and use it for the internal clock.
SUMMARY OF THE INVENTION
In accordance with the present invention, this objective is readily accomplished by means of a relatively low power, circuit real estate area-efficient, clock signal generator that detects the presence of an externally sourced clock, and then uses this clock as the clock for internal chip circuitry. The present invention is able to provide synchronization from a relatively low frequency range on the order of several Hertz (the lower limit being set by device leakage and size of an electrical energy storage capacitor) to hundreds of MHz (the upper limit being set by gate delays of the fabrication technology employed).
For this purpose, the present invention comprises a clock steering circuit in the form of a multiplexer having a first input to which an External Clock signal may be applied, and a second input to which an Internal Clock signal is applied. The external clock input port is further coupled to an inverting delay and to a first input of a logic circuit (e.g., an AND gate or a NAND gate). The output of the inverting delay is coupled to a second input of the logic circuit. The logic circuit has its output coupled to the control input of a switching device. The switching device has a current flow path therethrough coupled to a current source/sink, and in parallel with an electrical energy storage device, in the form of a capacitor that is also coupled to the current source/sink. The connection of the current source/sink and the capacitor is coupled to one input of a comparator, which has a second input coupled to a reference voltage. The output of the comparator is coupled to the select port of the multiplexer. The current supplied by the current source and the value of the capacitor are selected so that the time required for the comparator to reach its trip threshold is defined by N/f
internal clock frequency
. This allows the circuit to synchronize to an external clock that is as slow as 1/N times f
internal clock frequency
.
In operation, if an external clock having a frequency higher that a prescribed minimum or ‘override’ frequency is applied to the input port, the controlled switching device will be turned ON sufficiently often, to effectively prevent the capacitor from charging to a voltage value that will trip the comparator. For this ‘external override’ condition, the output of the comparator will remain in a first logical state, that will cause the External Clock signal to be coupled by the multiplexer to all chip logic circuitry requiring a clock signal. On the other hand, if no effective external clock is applied to the external clock input port the switching device is never turned on so that the capacitor is not discharged. This allows the voltage across the capacitor to attain a value that will trip the comparator, and change the select input to the multiplexer. In this case, the multiplexer couples the Internal Clock to the clock bus. It may be noted that external clock frequencies above 0 but less than 1/N would be outside the recommended design specification range and would produce an output clock signal that jitters between internal and external clock.


REFERENCES:
patent: 4982116 (1991-01-01), Lee
patent: 5142247 (1992-08-01), Lada et al.
patent: 5475324 (1995-12-01), Tomiyori
patent: 5604452 (1997-02-01), Huang
patent: 5828243 (1998-10-01), Bagley
patent: 6396324 (2002-05-01), Hsu et al.

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