Low-power analog-to-digital converter

Details Low-power analog-to-digital converter Low-power analog-to-digital converter

2001-01-19

2002-11-12

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S159000

Reexamination Certificate

active

06480133

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog-to-digital converter (A/D converter), and particularly relates to a high-speed A/D converter which can operate at a low voltage and which is reduced in circuit size (number of circuit elements) and in power consumption. The A/D converter according to the present invention is suitable to any product for performing digital signal processing, particularly to a product of a measuring instrument such as an FTT analyzer, a digital oscilloscope, or the like.
As a conventional fastest A/D converter, there is known a parallel-connected (flash) A/D converter. The circuitry of the A/D converter is formed by bit-resolution comparators numbering
2
to some power. For example, if the resolution is 8 bits, it is necessary to provide 256 (=2
8
) comparators and dispose a digital encoder with a large circuit quantity in the following stage of the comparators.
Therefore, in the conventional parallel-connected A/D converter, the circuit quantity and the power consumption become enormous, and the input capacitance also increases so that the high-frequency properties deteriorate. In a conventional circuit system used in the A/D converter, there is often used a voltage-mode circuit which carries out an operation in a voltage area. However, when the power supply voltage is reduced as integrated circuits are made finer, such a circuit system cannot deal with such a reduced voltage.
On the contrary, a folding-interpolation A/D converter has an advantage that the circuit quantity, the power consumption and the input capacitance are smaller than those of the parallel-connected A/D converter in spite of a high-speed property substantially equal to that of the parallel-connected A/D converter. As a prior art of such a folding-interpolation A/D converter, there is, for example, that which is disclosed in JP-A-8-149006.
SUMMARY OF THE INVENTION
As described above, the parallel-connected A/D converter has a problem that the circuit quantity, the power consumption and the input capacitance are large. On the other hand, the folding/interpolation A/D converter is a promising technique to solve such problems. However, most of proposed ones use a bipolar transistor circuit. Therefore, they cannot deal with a reduced power supply voltage, a finer integrated circuit, and reduced power consumption, satisfactorily.
Therefore, the present inventors made diligent investigation about a high-speed A/D converter, and at last developed a novel architecture of a high-speed A/D converter using a CMOS transistor circuit.
That is, the present invention is an evolution of a conventional folding/interpolation A/D converter. It is an object of the present invention to provide an A/D converter in which particularly an analog preprocessing circuit in an input stage of the A/D converter is devised to improve the A/D conversion properties, to make it possible to reduce a power supply voltage, and to provide fine and high-density integrated circuits.
According to a first aspect of the present invention, there is provided an A/D converter for converting an input analog signal into a Gray code of higher m bits and lower n bits, which comprises: m folding circuits for being supplied with analog signal pairs and reference voltage pairs and for outputting folded differential current pairs respectively; m first comparators for comparing the differential current pairs outputted by the folding circuits and for outputting the higher m bits of the Gray code; a plurality of sine wave generators for being supplied with the analog signal pairs and the reference voltage pairs and for outputting multi-phase sine wave pairs respectively; a current interpolation circuit for interpolating the multi-phase sine wave pairs and for outputting 2
n
sine wave pairs; 2
n
second comparators for comparing the sine wave pairs and for outputting binary data respectively; and a Gray code encoder for encoding the binary data into a Gray code of lower n bits; wherein the lower n bits of the Gray code are outputted from the Gray code encoder.
According to such an A/D converter, it is possible to reduce the total circuit quantity and the total power consumption on a large scale while keeping a speed substantially equal to that of the conventional parallel-connected A/D converter.
According to a second aspect of the present invention, in the above A/D converter according to the first aspect, preferably, the A/D converter further comprises: a track hold circuit for temporarily holding and outputting levels of the analog signal pairs in accordance with a clock signal; wherein the analog signal pairs are supplied, through the track hold circuit, to the folding circuits and the sine wave generators, the first and second comparators being operated synchronously with the clock signal.
According to such an A/D converter according to the second aspect, an A/D conversion error due to signal delay can be prevented from occurring, so that it is possible to improve the A/D conversion accuracy.
According to a third aspect of the present invention, in the above A/D converter according to the first and second aspects of the invention, preferably, the A/D converter further comprises: pre-amplifiers for amplifying potential differences between the analog signal pairs and the reference voltage pairs and for outputting differential voltage pairs respectively; wherein outputs of the pre-amplifiers are supplied to the folding circuits.
According to such an A/D converter according to the third aspect of the invention, it is possible to improve the A/D conversion accuracy.
According to a fourth aspect of the invention, in the above A/D converter according to the third aspect of the invention, preferably, the folding circuits includes: differential MOS transistor pairs having gates supplied with the differential voltage pairs respectively; a current source for supplying a first current to the differential MOS transistor pairs; and a current mirror circuit for supplying a second current to a pair of current channels; wherein drains of the differential MOS transistor pairs are cross-connected alternately to the pair of current channels so that folded differential current pairs are outputted from ends of the pair of current channels.
According to such an A/D converter, the voltage can be reduced by the current-mode CMOS arrangement.
According to a fifth aspect of the invention, there is provided an A/D converter for outputting a digital signal of m+n bits, which comprises: folding circuits for being supplied with differential analog signals and for outputting higher m bits of the digital signal respectively; sine wave generators for being supplied with the differential analog signals and for outputting lower n bits of the digital signal respectively; and a current interpolation circuit for interpolating outputs of the sine wave generators; the folding circuits including: at least one differential MOS transistor pair having gates supplied with differential voltage pairs which are differences between the differential analog signals and differential reference voltages, respectively; a current source for supplying a first current to the differential MOS transistor pairs; and a current mirror circuit for supplying a second current to a pair of current channels; wherein drains of the differential MOS transistor pairs are cross-connected alternately to the pair of current channels so that folded differential current pairs are outputted from ends of the pair of current channels.
It is possible to reduce the total circuit quantity and the total power consumption on a large scale while keeping a speed substantially equal to that of the conventional parallel-connected A/D converter. In addition, the voltage can be reduced by the current-mode CMOS arrangement.
According to a sixth aspect of the invention, in the A/D converter according to the fifth aspect, preferably, the A/D converter further comprises a current comparator for comparing the differential current pair and for outputting a Gray-coded digital signal.
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