Low power analog-to-digital converter

Details Low power analog-to-digital converter Low power analog-to-digital converter

2000-03-13

2001-09-11

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000, C341S161000, C341S118000, C341S158000

Reexamination Certificate

active

06288667

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY FUNDED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
Analog-to-digital converters (ADCs) have widespread application. One growing application is in battery operated, portable devices, such as for data conversion in portable video devices. This application requires relatively low power, high throughput and low precision. Illustrative parameters include a minimum of 8 bits of conversion with a throughput of 20 M samples/second. In order to make data conversion an insignificant part of the total system power drawn from the battery, power levels of less than a few milliwatts are desirable.
One conventional low power ADC architecture utilizes a plurality of pipelined, or series-coupled stages, with each stage converting one bit of data. Each stage includes a sample and hold circuit, an analog-to-digital converter, a digital-to-analog converter, a summing circuit and an amplifying circuit. The sample and hold circuit shift registers the analog sample and the analog-to-digital converter provides the output bit for the stage. The value of the output bit is converted back into an analog signal by the digital-to-analog converter and is subtracted from the input analog sample by the summing circuit. The difference signal is then scaled by the amplifying circuit and applied to a subsequent stage for conversion of the next most significant bit.
In order to limit noise, such as thermal noise, shot noise and flicker noise, to an acceptable level, the capacitance value used in circuit components must be greater than a predetermined minimum. As one example, where the thermal noise is limited to one-half of the least significant bit, the minimum capacitance can be found by:
1
2
⁢
LSB
=
V
R
2
P
+
1
=
3
⁢
kT
C
,
where V
R
is the input voltage range, P is the precision, k is Boltzmann's constant, T is the temperature, and C is the resulting minimum capacitance. This minimum capacitance dictates the current that the operational amplifiers must drive to achieve a given throughput which, in turn, dictates the power dissipated by the operational amplifiers. As a result, power dissipation for an illustrative 12 bit, 20 M samples/second ADC can be on the order of one-half watt.
Various techniques have been proposed to reduce the power dissipation associated with pipelined ADCs. These include the scaling of the sampling capacitance in each of the pipelined stages and resolution of more bits per stage which reduces the thermal noise capacitance requirements in later stages, both of which are described by D. W. Cline, et al. in “A Power Optimized 13-b, 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 &mgr;m CMOS,” IEEE Journal of Sold-State Circuits, vol. 31, no. 3, pp. 294-303, 1996. Another technique, which was proposed by P. C. Yu et al. in “A 2.5-V, 12-b, 5Msample/s Pipelined CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, 1996, is time multiplexing one operational amplifier to serve both the sampling and amplifying functions, which saves DC power.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an analog-to-digital converter having lower power dissipation than heretofore achieved.
It is a further object of the invention to provide such an analog-to-digital converter with suitable parameters for data conversion in portable video devices.
These and other objects of the invention are provided by an analog-to-digital converter (ADC) comprising a first device having an input port adapted to receive an analog voltage, a second device coupled to the first device and having an input port adapted to receive a predetermined digital control word, and a circuit for comparing the impedance across the second device to the impedance across the first device to provide each bit of the corresponding digital output word. In operation, a plurality of predetermined digital control words are applied to the second device sequentially in order to provide all of the bits of the corresponding digital output word.
Also provided is a logic circuit for determining the predetermined digital control words during a calibration process such that the predetermined digital control words compensate for non-linearities and other error-causing phenomena in components of the analog-to-digital converter. The predetermined digital control words are determined in response to the application of precision reference voltages to the input port of the first device and application of trial digital control words to the input port of the second device during the calibration process.
With this arrangement, the ADC has a significantly lower power dissipation than conventionally possible, such as on the order of 8 mW for a 12 bit, 20 Msamples/second converter. The lower power dissipation is achieved by eliminating the use of linear components in the converter, particularly operational amplifiers. Rather than using linear components to convert the analog input voltage, the predetermined digital control words generated during calibration and used during conversion to compensate for the circuit non-linearities, as well as other error-causing phenomena such as mismatched devices and self-induced supply noise. Stated differently, a set of “reference impedances” in the form of the predetermined digital control words is used during conversion, with the predetermined digital control words being based on the actual, non-linear and otherwise non-ideal performance of the ADC components. Lower power dissipation is also enhanced by use of the precision reference voltage only during the calibration process, as contrasted to conventional converters which use precision reference voltages during the conversion process.
Also described is a method for converting an analog voltage into a corresponding digital output word including the steps of applying the analog voltage to a first device, applying a predetermined digital control word to a second device coupled to the first device, determining whether the impedance of the first device is greater than the impedance of the second device, and providing a bit of the corresponding digital output word at a first logic level if the impedance of the first device is greater than the impedance of the second device and providing the bit of the corresponding digital output word at a second logic level if the impedance of the first device is less than the impedance of the second device. The method is repeated to provide all of the bits of the corresponding digital output word and further includes the step of determining the predetermined digital control words as a function of component non-linearities during a calibration process.
In one embodiment, each of the predetermined digital control words is determined by applying a precision reference voltage to the first device and sequencing through a plurality of trial digital control words until one is found which, when applied to the second device, causes the impedance of the second device to be just greater than the impedance of the first device. The applied trial digital control word is then stored as a predetermined digital control word.


REFERENCES:
patent: 4272760 (1981-06-01), Prazak et al.
patent: 4870341 (1989-09-01), Pihl et al.
patent: 4908621 (1990-03-01), Polonio et al.
patent: 4926175 (1990-05-01), Ishizawa et al.
patent: 5027116 (1991-06-01), Armstrong et al.
patent: 5122800 (1992-06-01), Philipp
patent: 5257026 (1993-10-01), Thompson et al.
patent: 5499027 (1996-03-01), Karanicolas et al.
patent: 5510789 (1996-04-01), Lee
patent: 5583501 (1996-12-01), Henrion et al.
patent: 5594439 (1997-01-01), Swanson
patent: 5594612 (1997-01-01), Henrion
patent: 5852415 (1998-12-01), Cotter et al.
patent: 5861829 (1999-01-01), Sutardja
patent: 5870041 (1999-02-01), Lee et al.
patent: 5990814 (1999-11-01), Croman et al.
David W. Cline, “A Power Optimized 13-b 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 &mgr;m CMOS”, IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 166-172.
Thomas Byungha

Affiliated with

Also associated with

Rating

Low power analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power analog-to-digital converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2449813