Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1990-02-13
1991-03-12
Fears, Terrell W.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523001, G11C 1140
Patent
active
049998153
ABSTRACT:
Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.
REFERENCES:
patent: 4763302 (1988-08-01), Yamada
patent: 4831597 (1989-05-01), Fuse
Barth, Jr. John E.
Drake Charles E.
Hovis William P.
Kalter Howard L.
Kelley, Jr. Gordon A.
Fears Terrell W.
International Business Machines - Corporation
Limanek Stephen J.
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