Low power adder for accumulation

Details Low power adder for accumulation Low power adder for accumulation

1995-06-07

1997-11-25

Ngo, Chuong D.

Boots, shoes, and leggings

364707, G06F 750, G06F 100

Patent

active

056919310

ABSTRACT:
A low power, adder-based circuit for accumulating small inputs is disclosed. Many applications running on large scale integrated circuits (LSIs) require small, two's complement inputs to be accumulated hundreds, or thousands, of times. Given the number of times such an accumulation is performed, it is essential that the LSI circuitry performing the accumulation operation is power efficient. It is also essential that the accumulator circuitry is compact and not overly complex to keep chip size and cost to a minimum. The present invention includes a input converter that shifts the inputs to be accumulated by a fixed positive amount, yielding a shifted input that is guaranteed to be a positive value. The adder then accumulates the positive shifted inputs. After all of the shifted inputs are accumulated, the adder adds a negative offset to the total to correct for the fixed positive mount added to each of the original inputs. The resulting circuit is power efficient because all of the values accumulated are positive, which minimizes the transition probability of bits manipulated by the adder. The resulting circuit also uses minimal chip real estate as it only needs one adder that performs both accumulation and offset correction.

REFERENCES:
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patent: 5375079 (1994-12-01), Uramoto et al.
patent: 5497341 (1996-03-01), Cohen
patent: 5504698 (1996-04-01), Su
Anantha P. Chandrakasan, Randy Allmon, Anthony Stratakos, Robert W. Brodersen, "Design of Portable Systems", IEEE 1994 Custom Integrated Circuits Conference, pp. 259-266.

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