Low powder CMOS circuit

Details Low powder CMOS circuit Low powder CMOS circuit

1998-10-30

2001-04-03

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C326S112000

Reexamination Certificate

active

06211725

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS circuit, and more particularly, to a low power CMOS circuit which is operable at a low power and has a low power consumption at standby.
2. Discussion of the Related Art
It is current trend that device sizes are in general scaled down for improving speeds, and a portable system operable on a battery requires both a low power and a high performance. In view of heat emission, the low power is increasingly considered important even in a mainframe design in which the performance has been considered the most important.
A gate delay(&tgr;pd) of an invertor can be expressed by the following equation (1).
τ
pd
=
C
L
·
Vdd
2
⁢
Ion
Where, C
L
denotes a load capacitance, Vdd denotes a power supply voltage, and Ion denotes a saturation current of an MOSFET.
A system power can be expressed by an equation (2) shown below.
a·f·C
L
·V
2
dd+Ioff·Vdd+Isc·f·Vda,
where, the term “a·f·C
L
·V
2
dd” represents an active power in which “a” denotes a activity factor, “f” denotes a clock frequency. The term “Ioff·Vdd” represents a standby power consumed by the Ioff. The last term “Isc·f·Vda” represents a power from a short circuit current flowing when a PMOS and an NMOS in an invertor gate are at turned on on the same time, which is negligible when Vdd is low. As can be know from equation (2), lowering the power supply voltage Vdd is the most efficient way to reduce the power. However, the lowering of the supply power voltage to reduce the power causes a speed reduction, which leads to a lowered threshold voltage for compensating the speed reduction, that results in an increased standby power coming from an increased subthreshold leakage current. In order to reduce this standby power, either a device fabricating technique or a circuitry technique may be improved, in which a subthreshold current reduction circuit or an MTCMOS circuit or a well biasing circuit may be used.
A background art CMOS circuit will be explained with reference to the attached drawings.
Referring to
FIG. 1
, a background art MTCMOS(MultiThreshold CMOS) circuit is provided with transistors of high threshold voltages and transistors of low threshold voltages. The high threshold voltage is an absolute threshold voltage equal to or higher than 0.5V and the low threshold voltage is an absolute threshold voltage equal to or below 0.4V. Or, when there is a threshold voltage difference greater than 0.1V, the higher one may be called as a high threshold voltage and the lower one may be called as a low threshold voltage. In the transistors of high threshold voltage, there are a first PMOS transistor PM
1
and a first NMOS transistor NM
1
. The first PMOS transistor PM
1
has one terminal applied of the power supply voltage VDD, the other terminal connected to a virtual power supply voltage VDDV, and a gate terminal applied of a standby signal S
1
. The NMOS transistor NM
1
has one terminal connected to a ground voltage, the other terminal connected to a virtual ground voltage GNDV, and a gate terminal connected to an inverted standby signal S
2
. The transistors of low threshold voltages are provided between the virtual power supply voltage VDDV line and the virtual ground voltage GNDV line. In the transistors of low threshold voltages, there are second, and third PMOS transistors PM
2
and PM
3
each having one terminal connected to the virtual power supply voltage line in common and connected in parallel for receiving signals S
4
, S
5
different from each other, and second, and third NMOS transistors NM
2
and NM
3
connected in series between the other terminals, which are connected in common, of the second, and third PMOS transistors PM
2
and PM
3
and the virtual ground voltage line for receiving signals S
4
, S
5
different from each other.
In an operation mode of the MTCMOS circuit, when a standby signal S
1
at ‘low’ and an inverted standby signal S
2
at ‘high’ are received, the first PMOS transistor PM
1
and the first NMOS transistor NM
1
are turned on, causing the virtual power supply voltage line and the virtual ground voltage line operative as actual power lines, with a reduction of a circuit resistance. On the contrary, in a standby mode, when a standby signal S
1
at ‘high’ and an inverted standby signal S
2
at ‘low’ are received, the first PMOS transistor PM
1
of a high threshold voltage and the first NMOS transistor NM
1
of a high threshold voltage are turned off, causing the virtual power supply voltage line VDDV and the virtual ground voltage line GNDV floated, so as to be operative by the power supply voltage and the ground voltage, without a leakage flow. The operation speed of the MTCMOS circuit and a power consumption in a standby mode of the MTCMOS circuit are dependent on widths and driving powers of the first PMOS transistor PM
1
and the first NMOS transistor NM
1
.
Referring to
FIG. 2
, the well biasing circuit, provided with transistors of low threshold voltages, having low gamma factors including a fourth PMOS transistor PM
4
and a fourth NMOS transistor NM
4
connected in series between a power supply voltage VDD and a ground voltage VSS and adapted to be operative in response to a same signal S
3
and each having a well adapted to receive a back bias voltage Vbs in a standby mode. In the aforementioned well biasing circuit, a well bias voltage is applied to the wells in a standby mode, to increase the threshold voltage, that reduces a standby power.
The aforementioned background art low power CMOS circuits have the following problems.
First, in the case of the MTCMOS circuit, because of the first, and second PMOS transistors of high threshold voltages, an operation route becomes complicated, a chip area is increased, and no data can be conserved during a standby mode.
Second, the well biasing circuit has a limitation in reducing a power consumption in a standby mode as the fourth NMOS transistor has an increase of a threshold voltage by 0.1V even if a −2V back bias voltage is applied thereto due to a low gamma factor, a coefficient representing an increase of a threshold voltage upon application of a back bias in an short channel device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a low power CMOS circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a low power CMOS circuit which can minimize a power consumption in a standby mode.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the low power CMOS circuit provided with CMOS device includes PMOS transistors having drains connected to a power supply voltage and NMOS transistors having sources connected to a ground voltage, both of the PMOS transistors and the NMOS transistors being adapted to be applied of a back bias voltage in a standby mode, wherein the PMOS transistors and the NMOS transistors are formed to have great gamma factors.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5892260 (1999-04-01), Okumura et al.
patent: 5909140 (1999-06-01), Choi
Mutoh, S. et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”,IEEE Journal of Solid-State Circuits, vol. 30, No. 8, pp. 847-854, 1995.
Kuroda, T. et al., “A 0.9V 150MHz 10mW 4mm2-D Discrete Cosine Transform Core Pro

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