Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2001-06-07
2003-03-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S678000
Reexamination Certificate
active
06528893
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor chip packages, and more specifically to low-pin-count chip packages and manufacturing methods thereof.
2. Description of the Related Art
FIG. 1
is a low-pin-count chip package
100
according to a preferred embodiment disclosed in R. O. C. Publication No. 348306 entitled “Device Having Resin Package And Method Of Producing The Same”. The low-pin-count chip package
100
includes a chip
110
sealed in a package body
120
. The active surface of the chip
110
is provided with a plurality of bonding pads
110
a
electrically connected to a plurality of connection pads
130
. The backside surface of the chip
110
is exposed from the package body
120
through a conductive adhesive layer
112
. The connection pads
130
are located at the periphery of the chip
110
and exposed from the lower surface of the package body
120
for making external electrical connection.
R. O. C. Publication No. 348306 entitled “Device Having Resin Package And Method Of Producing The Same” also discloses a method for making the low-pin-count chip package
100
. The method mainly utilizes a metal frame
170
(see
FIG. 2
) to fabricate a plurality of the low-pin-count chip packages
100
simultaneously. The method comprises the steps of: (A) applying a photoresist layer over one surface of the metal frame
170
, pattern transferring, and developing in a manner that areas on the metal frame
170
at which it is desired to form the connection pads
130
are not covered by the photoresist layer; (B) plating a layer of metal such as gold or palladium on the areas on the metal frame
170
without protection by the photoresist layer; (C) stripping the remaining photoresist; (D) attaching the backside surface of the semiconductor chip
110
onto the metal frame
170
through an adhesive layer wherein the active surface of the semiconductor chip is provided with a plurality of bonding pads
110
a;
(E) electrically coupling the bonding pads
110
a
on the semiconductor chip
110
to the corresponding connection pads
130
; (F) forming a package body over the semiconductor chip
110
. Finally, a separation step is performed to remove the metal frame
170
. As shown in
FIG. 2
, the separation step typically comprises selectively etching the metal frame
170
with the connection pads
130
remaining intact by an etching agent.
Since the package body
120
does not cover the exposed lower surface of the connection pads
130
, it can not firmly lock the connection pads
130
. Adhesion depends on the overall nature of the interface region. A method for promoting adhesion is increasing the area of the interface between the package body
120
and the connection pads
130
. However, since the connection pads
130
are formed by plating, the thickness thereof is limited (is proportional to the time for plating). Typically, thickness of the metal plating is only about 0.4 to 10.8 mils, which contributes quite little to the adhesion between the package body
120
and the connection pads
130
.
Moreover, the connection pads
130
are made of metal with good electrical conductivity such as copper but the package body
120
is made of insulating material such as epoxy molding compound. Accordingly, the bond between connection pads
130
and the package body
120
is relatively weak and the difference of the coefficient of thermal expansion (CTE) therebetween is very large. Because of the CTE mismatch, stresses are induced at the interface between the connection pads and the plastic package body as the conventional package experiences temperature cycling. The stresses, in turn, result in the delamination at the metal-plastic interface. When the delaminations had occurred at the plastic-metal interface, moistures from the environment are easy to penetrate into the plastic package body and accumulate in the delaminated area. Once moisture accumulates in the package, rapid temperature ramp-up will cause the moisture to vaporize and expand, thereby inducing an hygrothermal stresses in the delaminated area which causes the surrounding plastic package body to popcorn. One of the most common occurrence of package popcorning occurs when the package described above is surface-mounted to a printed wiring board during the Infra-Red reflowing process.
Therefore, there is a need for methods of making the low-pin-count chip package that allow a significant increase of the thickness of connection pads thereby increasing the area of the interface between the package body and the connection pads. Thus, by promoting the adhesion between the package body and the connection pads, the present invention provides such a method overcoming or at least reducing the problems as described above.
SUMMARY OF THE INVENTION
The present invention therefore provides a low-pin-count chip package comprising a plurality of connection pads electrically connected to a semiconductor chip wherein the connection pads are formed by etching such that they have a concave profile and a thickness that allows good adhesion to the package body.
Accordingly, in a first aspect, the present invention provides a low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. A package body is formed over the semiconductor chip and the connection pads in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This significantly increases the area of the interface between the package body and the die pad as well as the connection pads, and prolongs the path and time for moisture diffusion into the package thereby enhancing the “locking” of the die pad and the connection pads in the package body as well as promoting adhesion therebetween.
According to a second aspect, this invention further provides a method of producing a low-pin-count chip package. The method comprises the steps of: (A) providing a sheet carrier having a metal layer on one surface thereof; (B) applying a photoresist layer on the metal layer of the carrier sheet; (C) photoimaging and developing the photoresist layer so as to expose predetermined portions of the metal layer, (D) forming a metal coating on the exposed portions of the metal layer; (E) stripping the remaining photoresist; (F) etching areas on the metal layer without protection of the metal coating so as to form a die pad and a plurality of connection pads having a concave profile; (G) attaching a semiconductor chip onto the die pad; (H) electrically coupling the semiconductor chip to the connection pads; (I) forming a package body over the semiconductor chip and the connection pads; (J) removing the sheet carrier; and (K) forming a metal flash on the lower surface of the connection pads exposed from the package body.
REFERENCES:
patent: 5474066 (1995-12-01), Grolman
patent: 6001671 (1999-12-01), Fjelstad
patent: 6093584 (2000-07-01), Fjelstad
patent: 6102710 (2000-08-01), Beilin et al.
patent: 6136681 (2000-10-01), Razon et al.
patent: 6261864 (2001-07-01), Jung et al.
patent: 6342730 (2002-01-01), Jung et al.
R.O.C. Publication No. 348306, dated Nov. 7, 1985, entitled Device Having Resin Package And Method Of Producing The Same (English Abstract)
Jung Kyujin
Kang Kun-A
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