Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2001-08-30
2002-12-17
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S690000, C257S693000, C257S784000, C257S786000, C257S787000
Reexamination Certificate
active
06495909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor chip packages, and more specifically to low-pin-count chip packages and manufacturing methods thereof.
2. Description of the Related Art
FIG. 1
is a low-pin-count chip package
100
according to a preferred embodiment disclosed in R. O. C. Publication No. 348306 entitled “Device Having Resin Package And Method Of Producing The Same”. The low-pin-count chip package
100
includes a chip
110
sealed in a package body
120
. The active surface of the chip
110
is provided with a plurality of bonding pads
110
a
electrically connected to a plurality of connection pads
130
. The backside surface of the chip
110
is exposed from the package body
120
through a conductive adhesive layer
112
. The connection pads
130
are located around the periphery of the chip
110
and exposed from the lower surface of the package body
120
for making external electrical connection. Since the package body
120
does not cover the exposed lower surface of the connection pads
130
, it cannot firmly lock the connection pads
130
.
The connection pads
130
are usually made of metal with good electrical conductivity such as copper but the package body
120
is made of insulating material such as epoxy molding compound. Accordingly, the bond between connection pads
130
and the package body
120
is relatively weak and the difference of the coefficient of thermal expansion (CTE) therebetween is very large. Because of the CTE mismatch, stress is created at the interface between the connection pads and the plastic package body as the conventional package experiences temperature changes. The stress, in turn, results in the delamination of the metal-plastic interface. After the plastic-metal interface becomes delaminated, moisture from the environment diffuses through the plastic package body to the delaminated area. Once moisture accumulates in the package, rapid temperature increases will cause the moisture to vaporize and expand, thereby creating an internal pressure in the delaminated area which causes the surrounding plastic package body to crack. The most common occurrence of package cracking occurs when the conventional package described above is soldered to a substrate by IR reflow.
Further, since the package body
120
only seals one side of the chip
110
, moisture and/or ionic contamination from the atmosphere can sometimes penetrate through the bonding lines between the epoxy molding compound and the chip
110
, which can cause reliability problems, i.e. a greatly reduced chip operating life. This phenomenon is becoming more and more critical as the semiconductor industry moves towards packaging electronic devices in smaller and smaller packages.
SUMMARY OF THE INVENTION
The present invention therefore seeks to provide a low-pin-count chip package which overcomes, or at least reduces the above-mentioned problems of the prior art.
Accordingly, in a first aspect, the present invention provides a low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. A package body is formed over the semiconductor chip and the connection pads in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the path and time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body.
According to a second aspect, this invention further provides a method of producing a low-pin-count chip package. The method comprises the steps of: (A) forming a photoresist layer on a metal plate; (B) photoimaging and developing the photoresist layer so as to expose predetermined portions of the metal plate; (C) forming a protective metal flash on the exposed portions of the metal plate; (D) overplating a layer of conductive material on the protective metal flash so as to form a die pad and a plurality of connection pads having a T-shaped profile, wherein the “overplating” means that the plating of the conductive material is not stopped until the thickness thereof is greater than that of the photoresist layer; (E) forming a metal coating on the exposed surfaces of the die pad and the connection pads; (F) stripping the photoresist layer; (G) attaching a semiconductor chip onto the die pad; (H) electrically coupling the semiconductor chip to the connection pads; (I) forming a package body over the semiconductor chip and the connection pads; and (J) removing the metal plate.
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Jung Kyujin
Kang Kun-A
Advanced Semiconductor Engineering Inc.
Chambliss Alonzo
Cuneo Kamand
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