Low phase noise phase locked loops with minimum lock time

Details Low phase noise phase locked loops with minimum lock time Low phase noise phase locked loops with minimum lock time

2006-12-06

2009-02-03

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S034000, C331S17700V, C327S156000

Reexamination Certificate

active

07486147

ABSTRACT:
A phase locked loop with improved lock time is achieved using a controller coupled to receive a reference signal and operable to generate a frequency divider control signal based upon the reference signal to control operation of a frequency divider. The PLL further includes a phase frequency detector for producing an error signal indicative of a difference in phase or frequency between the reference signal and a feedback signal, a charge pump for generating a current pulse proportional to the error signal, a loop filter for filtering the current pulse to produce a control voltage and a voltage controlled oscillator for producing an oscillation based upon the control voltage. The frequency divider is coupled to receive the oscillation and is operable to divide the oscillation by a divide ratio to produce the feedback signal.

REFERENCES:
patent: 7064591 (2006-06-01), Humphreys et al.

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