Low phase noise clock multiplication

Details Low phase noise clock multiplication Low phase noise clock multiplication

1999-12-31

2001-05-08

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S119000

Reexamination Certificate

active

06229359

ABSTRACT:

FIELD OF THE INVENTION
The current invention is directed to a method of generating a clock signal that is an integral multiple of a fundamental frequency while introducing minimal additional time jitter or phase noise.
BACKGROUND OF THE INVENTION
There are many different methods of generating a clock that is an integral multiple of a fundamental frequency. One well known method is the use of a PLL and a frequency-phase detector with a feedback loop. Such devices are referenced in U.S. Pat. No. 5,809,291 and the book “Phase Locked Loops” by Floyd Gardner. One problem with phase locked loops is that the phase noise of the generated output signal is derived from the phase noise of the VCO which generates it, rather than from the low phase noise of the fundamental frequency oscillator which feeds it. This results in an interesting phenomenon whereby the phase noise of the output signal actually decreases very close to the fundamental frequency, where the lower noise and high loop gain of the error amplifier is able to produce an error signal which tracks the phase error of the VCO and feed this signal back into the noisy VCO, thereby making this part of the spectrum quieter. The VCO typically has a higher phase noise level than a crystal oscillator because the crystal oscillator has a much higher Q and is only able to operate in a very narrow range of frequencies, while the VCO has an intrinsically lower Q and can be modulated by small levels of electrical noise appearing on the control voltage input.
An alternate method of deriving a higher frequency signal from an input signal is the use of DLL (delay locked loop) oscillator, which comprises a chain of delay elements in a loop, each delay element controlled by a control voltage. Such systems are described in U.S. Pat. Nos. 5,818,270 and 5,920,211. In this type of system, the DLL is providing the intrinsic phase noise, and the system clock is merely a reference for the use of the comparator.
Another alternate method of deriving a higher frequency signal from an input signal involves the use of an exclusive OR gate with a delay line, as is described in U.S. Pat. No. 5,563,538. In this circuit, the objective is not the generation of a harmonic clock, but the extraction of a 2× clock from a clock-encoded optical signal of varying amplitude, typically from a photodiode of a communication system. In this reference, a delay line is combined with an exclusive OR gate to produce a 50% duty cycle signal at 2× the input frequency, and a SAW bandpass filter of high Q is provided afterwards to provide a sinusoidal output waveform at twice the output frequency.
OBJECTS OF THE INVENTION
A first object of the invention is the optimal generation of even harmonics from an input signal. A second object of the invention is the generation of a low phase noise harmonic which is derived from a fundamental input frequency source. A third object of the invention is the generation of even harmonics of an input signal whereby the duty cycle of the waveform is adaptively changed to maximize the output content of second harmonic power. A fourth object of the invention is the generation of a low phase noise output through the generation of second harmonic content of an input signal whereby the duty cycle of the input signal is varied to maximize the second harmonic content of the signal.
SUMMARY OF THE INVENTION
A periodic input signal having a period T is divided into a delayed and a normal signal. The delayed signal lags the normal signal by &pgr;/2 radians in phase or T/4 in time. The normal signal and the delayed signal are delivered to a switching element which may be an OR gate, an AND gate, or a D Flip Flop. The switching element creates an output duty cycle which is optimized for output power of the harmonic content of the desired signal, and may be the second harmonic of the fundamental frequency. A filter suppresses the fundamental frequency and passes on the harmonic energy to an output. Optionally, the output signal may be passed through an adaptive filter which detects a maximum level of second harmonic power, and provides an error signal to vary the delay element to produce an output with a maximum level of second harmonic signal energy.


REFERENCES:
patent: 4877974 (1989-10-01), Kamai et al.
patent: 5530387 (1996-06-01), Kim
patent: 5563530 (1996-10-01), Mukoujima
patent: 5809291 (1998-09-01), Mundz-Bustanate et al.
patent: 5818270 (1998-10-01), Hamza
patent: 5920211 (1999-07-01), Anderson et al.
patent: 6147525 (2000-11-01), Mitani et al.

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