Low parasitic FET topology for power and low noise GaAs FETs

Details Low parasitic FET topology for power and low noise GaAs FETs Low parasitic FET topology for power and low noise GaAs FETs

1990-05-02

1991-06-11

Prenty, Mark

357 68, 357 55, H01L 2980, H01L 2348, H01L 2906

Patent

active

050236776

ABSTRACT:
A gallium arsenide FET having a gate pad with interleaved source and drain regions on two opposing sides of the gate pad, a plurality of gate fingers extending from the gate pad and disposed between each adjacent pair of a source region and a gate region.

REFERENCES:
patent: 3969745 (1976-07-01), Blocker, III
patent: 4298879 (1981-11-01), Hirano
patent: 4935805 (1990-06-01), Calviello et al.

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