Low P+ contact resistance formation by double implant

Details Low P+ contact resistance formation by double implant Low P+ contact resistance formation by double implant

1992-01-02

1993-07-06

Chaudhuri, Olik

Heating

Processes of heating or heater operation

Of heating a fluid

437 44, 437950, 257 24, H01L 21265

Patent

active

052253570

ABSTRACT:
The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less is done by providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric. Implanting of BF.sub.2 + ions and B11+ ions sequentially by using the pattern as a mask. The structure is annealed at more than about 850.degree. C. to complete the PMOS integrated circuit. This method results in lower contact resistance to the P+ regions and lower sheet resistance for higher speed CMOS integrated circuits at minimal increase of manufacturing cost.

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patent: 4786609 (1988-11-01), Chen
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5073514 (1991-12-01), Ito et al.
patent: 5089432 (1992-02-01), Yoo
patent: 5091763 (1992-02-01), Sanchez
Sze in VLSI Technology, McGraw-Hill Co., N.Y. 1988, pp. 350, 362 and 363.
IBM Technical Disclosure Bulletin, vol. 29, No. 7, Dec. 1986, p. 3132.

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