Low order first bit serial finite field multiplier

Details Low order first bit serial finite field multiplier Low order first bit serial finite field multiplier

1995-03-31

1997-10-21

Mai, Tan V.

Boots, shoes, and leggings

G06F 700

Patent

active

056803400

ABSTRACT:
A k-bit serial finite field multiplier circuit for multiplying a predetermined number of elements Wj in a finite field GF(2.sup.m) by a respective predetermined constant and summing the resulting products. The bits of the elements Wj are loaded serially, low order first, into the bit serial multiplier. For k greater than 1, the bits of the elements Wj are divided into k interleaves and processed by the multiplier k bits at a time. The multiplier comprises k number of linear feedback shift registers for performing the multiplication such that after m/k clock cycles the content of the shift registers is the sum of the products:

REFERENCES:
patent: 4777635 (1988-10-01), Glover
patent: 4891781 (1990-01-01), Omura
patent: 5210710 (1993-05-01), Omura
"Architectures for Exponentiation in GF(2.sup.n)," Beth et al. (No date).

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