Low or no-force bump flattening structure and method

Details Low or no-force bump flattening structure and method Low or no-force bump flattening structure and method

2002-01-07

2004-01-06

Elve, M. Alexandra (Department: 1725)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S772000, C257S692000, C257S738000

Reexamination Certificate

active

06674647

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to semiconductor manufacturing, and more particularly, to placement of chips on substrates.
BACKGROUND OF THE INVENTION
In semiconductor manufacturing, methods have developed for attaching and connecting components of semiconductor devices. Certain conventional techniques have been developed for using solder bumps on a chip to connect the chip to a substrate. E.g., U.S. Pat. No. 4,940,181, in which multiple layered cavities are formed in the substrate for receiving solder bumps on a chip.
However, while some conventional procedures for connecting a chip to a substrate such as a laminate are known, those procedures are imperfect. For example, in a manufacturing context, components such as chips may skew after placement. Such skewing may be caused by using a flux that is not tacky enough to hold a chip well in position. Attempts to correct this holding problem involve formulating a tackier flux. However, a tackier flux may present other problems. Some problems associated with using flux are mentioned in U.S. Pat. No. 5,558,271 to Rostoker, for “Shaped, Self-Aligning Micro-Bump Structures” issued Sep. 24, 1996. Also, the lighter a chip is, the more difficulty that is presented in holding components after normal processing.
Some problems of current bump-flattening methods arise from the force per bump, e.g., the force associated with 5 mil-bump production is about 124 grams or about ¼ pound per bump, which may be sufficiently high stress to damage the laminate under the bump. The force can be applied, for example, by hammering or by static force. Conventional methods apply about 500-600 pounds of force on 2000 input/outputs (I/Os) on the laminate, which is a relatively substantial force, application of which can result in damage to devices produced by such methods. Such methods in which force is so applied are referred to herein as “contact” bump-forming methods.
Further problems arise from conventional production methods. Currently, eutectic solder (such as 63/37 solder) compatible with a circuit board is provided on a circuit board. A small volume of solder paste is stenciled or screened onto pads on a substrate, followed by a reflow, to produce domes, onto which a chip may be provided. From such a construction, contact often is insufficient, resulting in chip solder (such as C4) falling off or skewing before or during reflow resulting in solder electric shorting. Also, in conventional production, solder paste (which is tacky) is provided on pads, after which components in paste are provided and the components stick during reflow. However, such a method cannot be used with very small features, such as bumps on the order of 5 mils.
Commercial manufacturing currently balances all of these problems and other requirements for device attachment by contacting flat spots with tiny bumps. Such methods are highly dependent on the absence of jarring, and such movement can easily ruin the chip to substrate alignment. Thus, methods for contacting a chip and a substrate not suffering from the problems mentioned above have been sought, but chip-to-substrate contacting remains problematic.
SUMMARY OF THE INVENTION
By providing reverse patterns of raised shapes and recesses respectively on a chip and a substrate to be connected to each other, reliable contact between the chip and substrate may be achieved, with other advantages. Skewing after placement of a chip on a substrate is minimized by methods according to the invention. Advantageously, the relatively high forces associated with contact methods of bump production are avoided. The invention does not rely on flat bumps, and thus chip-to-substrate contact is not as subject to being jarred apart. Adhesive-containing flux is not needed, and thus problems associated with high solids flux can be avoided.
In order to accomplish these and other objects of the invention, the present invention in a preferred embodiment provides a self-aligning manufacturing method for combining a substrate with a chip, comprising: (A) on a substrate surface, providing a pattern; (B) on a chip surface, providing a reverse pattern to the patterned substrate, raised recesses and raised shapes being included in said pattern and said reverse pattern; (C) aligning the pattern and the reverse pattern. The invention also provides for combining the substrate and the chip. In a further surface mount technology (SMT) embodiment, the substrate and the chip are combined at a temperature of between about 50 to 150° C. Laser ablating may be used for forming recesses and/or for removing volume from raised shapes.
In another preferred embodiment, the invention provides electronic packages comprising a substrate contacting a chip through raised recesses counterpart to raised shapes.
The invention further includes (i) on the substrate providing a plurality of conductive pads, and on each pad providing a solder region to form a pattern of solder regions on the substrate; and (ii) on the chip, providing a plurality of solder chip contacts in a reverse pattern to the pattern of solder regions on the substrate. The pattern of solder regions on the substrate may be a pattern of solder regions, and the reverse pattern on the chip may be a pattern of solder bumps. The pattern of solder regions on the substrate may be a pattern of solder bumps, and the reverse pattern on the chip may be a pattern of raised solder recesses.
Further details of the inventive methods and products include the following. Raised recesses, raised shapes or a combination of raised recesses and raised shapes may protrude from the substrate. Raised recesses protruding from the substrate may comprise a plurality of conductive pads each having a recess therein. Raised shapes, raised recesses, or a combination of raised shapes and raised recesses may protrude from the chip. The invention also provides for the raised shapes and raised recesses to be personalized-fitting.
The inventive methods and products in a preferred embodiment include a softer solder (such as a high lead C4 solder) and a harder solder (such as a eutectic solder), wherein the softer solder is formed into the harder solder.


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