Fishing – trapping – and vermin destroying
Patent
1994-01-12
1995-07-04
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437154, H01L 21335
Patent
active
054299640
ABSTRACT:
A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.
REFERENCES:
patent: 4191603 (1980-03-01), Garbarino et al.
patent: 4375999 (1983-03-01), Nawata et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4532534 (1985-07-01), Ford et al.
patent: 4584025 (1986-04-01), Takaoka et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4819044 (1989-04-01), Murakami
patent: 4974059 (1990-11-01), Kinzer
patent: 4982249 (1991-01-01), Kim et al.
patent: 5016066 (1991-05-01), Takahashi
patent: 5034346 (1991-07-01), Alter
patent: 5094900 (1992-03-01), Langley
patent: 5171699 (1992-12-01), Hutter et al.
patent: 5268586 (1993-12-01), Mukherjee et al.
patent: 5298442 (1994-03-01), Bulucea et al.
Takemura, H. "BSA Technology for Sub-100nm Deep Base Bipolar Transistors," IEEE, (1987) p. IEDM87-375.sup.+.
Antognetti, Power Imtegrated Circuits: Physics, Design, and Applications (McGraw-Hill Book Co.), 1986, pp. 3.14-3.27.
Baliga, Modern Power Devices (Wiley-Interscience), 1987, pp. 62-131.
"SMP60N06, 60N05, SMP50N06, 50N05, N-Channel Enhancement Mode Transistors," MOSPOWER Data Book, Siliconix inc., 1988, pp. 4-423-4-426.
Chang Mike
Chen Jun W.
Hshieh Fwu-Iuan
Owyang King
Pitzer Dorman C.
Carroll David H.
Chaudhuri Olik
Meetin Ronald J.
Mulpuri S.
Siliconix incorporated
LandOfFree
Low on-resistance power MOS technology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low on-resistance power MOS technology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low on-resistance power MOS technology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-759666