Low offset voltage AlInAs/GaInAs heterostructure-confinement bip

Details Low offset voltage AlInAs/GaInAs heterostructure-confinement bip Low offset voltage AlInAs/GaInAs heterostructure-confinement bip

1997-09-15

1999-11-02

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

257197, H01L 29737

Patent

active

059775726

ABSTRACT:
The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction.

REFERENCES:
patent: 5329145 (1994-07-01), Nakagawa
patent: 5404028 (1995-04-01), Metzger et al.
patent: 5598015 (1997-01-01), Tanoue et al.
patent: 5604356 (1997-02-01), Shiraishi

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