Low offset unity gain buffer amplifier

Details Low offset unity gain buffer amplifier Low offset unity gain buffer amplifier

1991-06-18

1993-06-08

Mottola, Steven

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

330267, H03F 326

Patent

active

052183211

ABSTRACT:
A buffer amplifier configuration simultaneously reduces d.c. voltage offsets through the signal flow path between its input and output and maintains a high input impedance and a low output impedance. In a preferred embodiment, high input impedance is achieved by coupling the input transistor's collector to a high impedance current source, which is coupled to one of the buffer's power supply rails. The emitter of the input transistor is coupled to the input terminal and its base of the base of a like polarity bipolar output transistor, the emitter of which is coupled to an output terminal and the collector of which is coupled to one supply rail. Since both the input and output transistors are of the same polarity type (so that they can be reasonably well matched during manufacture) and have their base-emitter junctions connected back-to-back between the input and output terminals, they impart effectively no Vbe-based d.c. offset voltage through the buffer. To ensure a high input impedance regardless of output load and output stage gain an isolating emitter-follower transistor stage is preferably coupled between the collector of the input transistor stage and the base of the output transistor stage.

REFERENCES:
patent: 4525682 (1985-06-01), Lai et al.
patent: 4639685 (1987-01-01), Saller et al.

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