Low offset CMOS comparator circuit

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

Patent

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Details

307299B, H03K 524

Patent

active

046021680

ABSTRACT:
A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.

REFERENCES:
patent: 4429234 (1984-01-01), Streit

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