Low noise vertical variable gate control voltage JFET device...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S134000, C257S135000, C257S260000, C257S263000, C257S265000, C257S272000, C257SE31073

Reexamination Certificate

active

07598547

ABSTRACT:
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

REFERENCES:
patent: 4939099 (1990-07-01), Seacrist et al.
patent: 6525390 (2003-02-01), Tada et al.
patent: 6861678 (2005-03-01), Howard et al.
patent: 6909125 (2005-06-01), Howard et al.
patent: 2008/0054312 (2008-03-01), Higashida
Pending U.S. Appl. No. 11/035,292, Howard et al., “Double diffused Vertical JFET”.
Pending U.S. Appl. No. 11/127,991, Howard et al., “Implant-controlled-Channel Vertical JFET”.

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