Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
1999-06-01
2001-01-23
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S573000, C257S592000, C257S616000
Reexamination Certificate
active
06177717
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to vertical bipolar transistors, especially those intended to be integrated in high-frequency very-large-scale-integration (VLSI) technologies. In particular, the invention relates to the characteristics and production of the emitters for these transistors.
BACKGROUND OF THE INVENTION
In polysilicon-emitter bipolar technologies, the emitter results from a deposition of polysilicon which can be carried out in a conventional oven followed by a doping operation. As a variant, the emitter may be doped in situ in a chemical vapor deposition (CVD) reactor. In both cases, an oxide layer is present at the emitter/base interface. This layer limits the hole current in the base (injected electrons continue to flow due to the tunnel effect). This helps to obtain a sufficient current gain (I
c
/I
b
).
However, these polysilicon-emitter transistors have certain drawbacks. First of all, they exhibit low-frequency noise which results in low-frequency fluctuations in the transistor current. This is even more troublesome in the case of radio frequency circuits incorporating such transistors for separating two close carriers. Furthermore, this is troublesome in the case of oscillators. Moreover, the dimensional characteristics of the oxide layer at the base/polysilicon-emitter interface have an influence on the static parameters of the transistor, especially its gain. However, it is particularly difficult to guarantee identical characteristics for oxide interfaces of all the transistors of several batches, this being especially so when the surface of the emitters varies. Consequently, it is particularly difficult to obtain uniform characteristics in all the transistors produced, whatever the surface of their emitter.
SUMMARY OF THE INVENTION
An object of the invention is to overcome these problems.
One object of the invention is to reduce the low-frequency noise while still retaining acceptable static parameters, and especially a correct current gain.
Another object of the invention is to allow better uniformity of the characteristics of the transistors to be obtained, whatever the surface of their emitter.
A further object of the invention is to provide a bipolar transistor in which the doping of the emitter allows both a high electron injection efficiency and good siliciding of the upper surface of the emitter.
The invention therefore provides a process for fabricating a vertical bipolar transistor, comprising a step of producing an intrinsic collector, for example by epitaxial growth or implantation, on an extrinsic collector layer buried in a semiconductor substrate. Furthermore, the process includes a step of producing a lateral isolation region surrounding the upper part of the intrinsic collector and of producing an offset extrinsic collector well, and a step of producing an SiGe (Silicon-Germanium) heterojunction base lying above the intrinsic collector and above the lateral isolation region. The step of producing the SiGe heterojunction base comprises the non-selective epitaxial growth of a stack of layers comprising at least one SiGe layer, for example, an SiGe layer encapsulated by two silicon layers or else an SiGe layer on top of a silicon layer, and a step of producing an in-situ doped emitter comprising epitaxial growth on a predetermined window of the surface of the stack (“emitter window”). The window lies above the intrinsic collector, so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the upper layer of the stack, for example, the silicon of the upper encapsulation layer of the stack.
In other words, the invention provides a way of producing an epitaxially grown single-crystal emitter directly on the “base” (in fact, the emitter/base junction defining the upper part of the intrinsic base lies in the upper encapsulation layer) so as to avoid the problem of the presence of an interfacial oxide layer. Consequently, the single-crystal emitter grown epitaxially, which means that there is no interfacial oxide, results in better uniformity of the characteristics of the transistors, whatever the surface of the emitters.
Moreover, it has been observed that such transistors with an emitter which is grown epitaxially directly on the base, and consequently which avoids the problem of interfacial oxide, exhibited appreciably reduced low-frequency noise. Furthermore, the presence of a silicon-germanium heterojunction base makes it possible, in combination with an emitter grown epitaxially directly on the base, to compensate to an acceptable extent for the loss of gain caused by the disappearance of the interfacial oxide layer.
Finally, the use of in-situ doping of the emitter, in combination with a single-crystal emitter, makes it possible, when producing the emitter, to gradually vary the amount of dopant while the emitter is being grown. This makes it possible, as will be seen in detail below in one particularly advantageous method of implementation, to obtain a higher dopant concentration in the bottom of the emitter than in the top of the emitter. This advantage is not possible with a polycrystalline emitter since the dopant is naturally distributed within the polysilicon because of the presence of the grain boundaries.
According to one method of implementing the invention, the step of producing the emitter comprises a first phase comprising the deposition of a silicon dioxide first layer on the surface of the stack, the deposition of a silicon nitride second layer on the silicon dioxide first layer, the etching of a zone corresponding to the position of the emitter window, in the silicon nitride layer, stopping the etching on the silicon dioxide first layer, then chemically deoxidizing the zone so as to obtain a silicon surface having a concentration of oxygen atoms of less than 10
15
/cm
3
in the window. The step of producing the emitter comprises a second phase comprising the exposure of the semiconductor block obtained at the first phase to a gas mixture of silane and of dopants in a non-oxidizing controlled atmosphere, for example, under vacuum, in an ultraclean CVD reactor well known to those skilled in the art.
Thus, the invention allows the use of conventional polysilicon deposition conditions in an ultraclean CVD reactor. However, the silicon grows in single-crystal form on the base because of the chemically clean character of the window in the base.
According to a first variant of the invention, after the second phase, a silicon layer is obtained which is of single-crystal form at least above the window and which is etched so as to form an emitter comprising an upper region wider than the window, this region bearing on part of the silicon nitride layer. Isolating spacers are then formed which are in contact with the vertical walls of the upper region wider than the emitter.
According to another variant of the invention, the first phase comprises the deposition of a thick silicon dioxide third layer on the silicon nitride second layer and preliminarily etching a region, corresponding to the position of the zone and consequently of the emitter window, in the silicon dioxide third layer, stopping on the silicon nitride second layer, so as to obtain, after the first phase, a semiconductor block comprising a cavity, of the same width as the window, in the stack of the three insulating layers. After the second phase, in other words, after epitaxial growth of the emitter, the cavity is filled by the epitaxial growth, the silicon dioxide third layer is etched on each side of the emitter block formed in the cavity and isolating spacers are formed which are in contact with the vertical walls of the emitter.
In other words, according to this variant of the invention, a shorter distance is obtained between the edge of the emitter and the implanted zone of extrinsic base, thereby helping to further reduce the base resistance as well as the base-collector capacitance. Furthermore, this shorter distance is controlled by a single photolithography level.
According to one me
Chantre Alain
Dutartre Didier
Guette Francois
Laurens Michel
Marty Michel
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhuri Olik
Galanthay Theodore E.
Pham Hoai
STMicroelectronics S.A.
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