Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-12-14
2002-08-27
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S314000, C327S530000
Reexamination Certificate
active
06441593
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing a regulator device generally and, more particularly, to a method and/or architecture for implementing a low noise switching regulator.
BACKGROUND OF THE INVENTION
Several conventional approaches for implementing regulator circuits have been developed. Regulator circuits connect one supply voltage (e.g., an external supply voltage) with another voltage (e.g., an internal supply voltage). Referring to
FIG. 1
, a circuit
10
implementing one such conventional approach is shown. The circuit
10
may be easily implemented and is area efficient. However, the circuit
10
has the disadvantages of a large voltage overshoot when operating with a high external supply voltage VPWRI. As large currents build up (as in the case of high external supply voltages), the ohmic drop (i.e., IRDROP) across the resistance R limits the gate drive of the switch S, reducing the total current. The reduction of current may not be sufficient and may result in higher overshoot. The resistor R is chosen such that little impact occurs to performance at a low operating range of the internal supply voltage VPWR.
In the circuit
10
, the series resistance R is sized such that a low external power supply voltage (VPWRI) does not compromise the internal voltage (VPWR) under high current conditions. For low external supply voltages, the current drop (IRDROP) due to the series resistance R is not significant. At higher external voltages, when the switch S turns on in response to a load condition, a sudden current can flow tending to equalize the internal supply voltage to the external supply voltage. The current flow causes an ohmic voltage drop across the resistor R.
The increased ohmic drop lowers the gate to source voltage VGS seen by the switch S. In the absence of the resistor R, the switch S can see all the gate to source voltage VGS from the external supply VPWRI to the ground. With the series source resistance, the switch S has a lower gate to source drive which operates at a lower current. Operating at a lower current does not compromise performance on a lower power supply voltage but can reduce peaking current at higher power supply voltage. A wide voltage range is generally undesirable with the circuit
10
but may be suitable for some applications.
Referring to
FIG. 2
, a circuit
20
of another conventional approach for implementing a regulator is shown. The circuit
20
uses a current source I in series with the PMOS switch S. The circuit
20
may have better, but still limited, performance compared with the circuit
10
. A large de-coupling capacitor Cl is implemented to suppress a coupling effect of the circuit
20
. The circuit
20
has the disadvantage of requiring a large die area. The circuit
20
also consumes DC current, which is generally undesirable.
Consider the circuit
20
, for example, when 100 mA is required. The internal supply voltage VPWR must be at a certain voltage. The current source must handle the current regardless of the external voltage VPWRI. Even if the external voltage VPWRI were to change between a normal 2.3 volts to a higher 3.7 volts, the current source still must provide the same current through the biased PMOS series device.
A disadvantage of the conventional implementation
20
is that the bias that controls the current source is affected by the transient response of the switch S. The effect is partially in response to the gate of the current source in series with switch S being modulated by the transient. A large capacitance can be added to power or ground to decouple the gate for minimum modulation on the gate. Reducing the modulation can provide a constant current through the switch S. Thus, the additional capacitance is effective in controlling the current.
As the external supply voltage VPWR increases the current is still limited by the current source. A typical approach for implementing a large current source is by mirroring the bias voltage from a smaller device supporting a small current. During a transient event (i.e., turn ON or OFF of the switch S), the drain of the current limiting device (N*W) drops and capacitively couples the capacitor C
2
to the mirror bias voltage. Such capacitive coupling has the undesirable effect of making the current source go into overdrive, resulting in large currents. A large decoupling capacitance C
1
may be used to lower the effect of coupling. An alternative solution is to provide a coupling effect that is equal and opposite in direction, to produce a net zero charge transferred to the bias node. The circuit
20
is costly to implement, requires significant die area, and has increased design complexity.
The conventional circuits
10
and
20
have disadvantages that include (i) large voltage overshoot on a regulated voltage supply, (ii) large di/dt noise which affects circuit performance, (iii) considerable cost and/or (iv) a large die area impact.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first device and a second device. The first device may be connected to a first supply voltage. The second device may be connected (i) in series with the first device and (ii) to a second supply voltage. The first device is generally biased to provide enhanced noise suppression performance. The second device is generally configured to switch between the first and second supply voltages.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a low noise switching regulator that may (i) have excellent noise suppression; (ii) deliver optimal performance; (iii) provide an open loop regulator in series with a switching regulator to provide enhanced noise performance; (iv) provide an open loop regulator including a native (or depletion) device; (v) provide a low noise switching regulator; and/or (vi) reduce voltage ranges of an internal regulator switch.
REFERENCES:
patent: 5422562 (1995-06-01), Mammano et al.
patent: 5553030 (1996-09-01), Tedrow et al.
patent: 5563501 (1996-10-01), Chan
patent: 5734277 (1998-03-01), Hu et al.
patent: 6046896 (2000-04-01), Saeki et al.
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6097235 (2000-08-01), Hsu et al.
patent: 6184670 (2001-02-01), Mulatti et al.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Patel Rajnikant B.
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