Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2011-07-12
2011-07-12
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185250, C365S185120, C365S185110, C365S185170, C365S185020, C365S185330
Reexamination Certificate
active
07978526
ABSTRACT:
In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
REFERENCES:
patent: 4785427 (1988-11-01), Young
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6490199 (2002-12-01), Lee et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 7046568 (2006-05-01), Cernea
patent: 7173854 (2007-02-01), Cernea et al.
patent: 7376030 (2008-05-01), Cernea
patent: 7447079 (2008-11-01), Nguyen et al.
patent: 7593265 (2009-09-01), Nguyen et al.
patent: 2001/0014035 (2001-08-01), Briner
patent: 2002/0172076 (2002-11-01), Marotta et al.
patent: 2004/0125651 (2004-07-01), Toda
patent: 2005/0169082 (2005-08-01), Cernea
patent: 2005/0219905 (2005-10-01), Watanabe
patent: 2006/0034122 (2006-02-01), Betser et al.
patent: 2006/0140007 (2006-06-01), Cernea et al.
patent: 2007/0153604 (2007-07-01), Tsao et al.
patent: 2009/0168540 (2009-07-01), Nguyen et al.
patent: 0 974 976 (2000-01-01), None
patent: 1 288 964 (2003-03-01), None
patent: 1 288 964 (2003-03-01), None
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2008/087262, mailed on Apr. 1, 2009, 13 pages.
EPO, “Examine's Substantive Report,” corresponding European Patent Application No. 08 867 382.7, mailed on Nov. 11, 2010, 2 pages.
Lee Seungpil
Mui Man Lung
Nguyen Hao Thai
Davis , Wright, Tremaine, LLP
SanDisk Corporation
Tran Andrew Q
LandOfFree
Low noise sense amplifier array and method for nonvolatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low noise sense amplifier array and method for nonvolatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low noise sense amplifier array and method for nonvolatile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2738835