Low noise phase locked loop with a high precision lock detector

Details Low noise phase locked loop with a high precision lock detector Low noise phase locked loop with a high precision lock detector

2006-07-13

2008-09-02

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000

Reexamination Certificate

active

07420428

ABSTRACT:
A phase lock loop (PLL) includes a voltage controlled oscillator (VCO) for providing a VCO output signal. A first phase/frequency detector (PFD) for providing a first voltage tuning signal is included for controlling a frequency of the VCO output signal by comparing a first reference signal to the VCO output signal. A second phase/frequency detector (PFD) for providing a second voltage tuning signal is included for controlling the frequency of the VCO output signal by comparing a second reference signal to the VCO output signal. The first and second voltage tuning signals provide, respectively, first and second gains of frequency per volt for controlling the frequency of the VCO output signal. The first voltage tuning signal has a higher gain than the second voltage tuning signal. The first voltage tuning signal provides coarse frequency control of the VCO output signal and the second voltage tuning signal provides fine frequency control of the VCO output signal.

REFERENCES:
patent: 4542351 (1985-09-01), Okada
patent: 6803827 (2004-10-01), Kenney et al.
patent: 6856202 (2005-02-01), Lesso
patent: 0 278 079 (1988-08-01), None

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