Low noise output buffer circuit

Details Low noise output buffer circuit Low noise output buffer circuit

1988-08-18

1989-11-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 307263, 307264, H03K 1716, H03K 19094, H03K 513

Patent

active

048809977

ABSTRACT:
A buffer circuit with controlled output switching rate suitable to suppress ground or power supply line voltage spikes attributable to current surges. The voltage driving the gate electrode of the selected CMOS inverter output transistor is controlled in rate of rise using three parallel connected sources of charging current. The first source of current is enabled immediately following the step input signal to provide a relatively high initial rate of current flow and corresponding voltage rise on the gate electrode of the output transistor, but is self-disabled at approximately half the supply voltage by threshold loss and body effect on the transistor supplying the first source of current. The succeeding time interval is characterized by a slow rate of rise of the output transistor gate voltage attributable to a small but continuous source of current to the output transistor gate electrode node. The concluding interval is characterized by a high rate of current flow to the gate electrode node, but is enabled by feedback responsive to having the output node approach the final logic level. The circuit is suitable for suppressing both ground line and power supply line voltage spikes, and is further capable of being implemented in a tri-state configuration with minimum added complexity.

REFERENCES:
patent: 4612466 (1986-09-01), Stewart
patent: 4777389 (1988-10-01), Wu et al.
patent: 4779013 (1988-10-01), Tanaka
patent: 4783601 (1988-11-01), Hartgring et al.
patent: 4785201 (1988-11-01), Martinez
patent: 4825099 (1989-04-01), Barton
patent: 4827159 (1989-05-01), Naganuma

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