Low-noise output buffer circuit

Details Low-noise output buffer circuit Low-noise output buffer circuit

1991-07-25

1992-09-08

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307572, H03K 500

Patent

active

051461200

ABSTRACT:
A low-noise output buffer circuit of this invention comprises a P-channel MOSFET having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor having a collector connected to the power source potential, an emitter connected to an output terminal and a base connected to the drain of the P-channel MOSFET, and a diode having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.

REFERENCES:
patent: 4547686 (1985-10-01), Chen
patent: 4791321 (1988-12-01), Tanaka et al.
patent: 4877975 (1989-10-01), Ueno
patent: 5059824 (1991-10-01), Ueno
Report of The 1990 IEICE Spring Conference, vol. 5, pp. 5-189 C-625 "Proposition of Base-Biased BiCMOS for Low Voltage Operation".
Patent Abstract of Japan, vol. 13, No. 268 (E-755) (3616) Jun. 20, 1989.
D. M. Taub, "IBM Technical Disclosure Bulletin", vol. 8, No. 1, Jun. 1965.

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