Low noise magneto-resistive read head preamplifier

Details Low noise magneto-resistive read head preamplifier Low noise magneto-resistive read head preamplifier

2000-03-24

2002-05-28

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S292000, C360S046000, C360S067000, C360S068000

Reexamination Certificate

active

06396346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of information storage, and more particularly to hard disk drive magneto-resistive head preamplifiers.
2. Description of the Prior Art
The need for larger and faster mass storage devices continues to increase as computer hardware and software technology continues to progress. Electronic databases and computer applications such as multimedia applications, for example, require ever increasing amounts of disk storage space.
Hard disk drive (HDD) technology continues to evolve and advance in order to meet these ever increasing demands. U.S. Pat. No. 5,831,888, entitled Automatic Gain Control Circuit, and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage and is incorporated by reference herein in its entirety. An HDD performs write, read and servo operations when storing and retrieving data. During a read operation, the appropriate hard disk sector to be read is located and data that has been previously written to the disk is read. A read/write head senses the changes in the magnetic flux of the disk platter and generates a corresponding analog read signal. A read channel receives the analog read signal, conditions the signal and detects “zeros’ and “ones” from the signal.
Hard disk drives are one type of disk storage that are particularly used in modem personal computers. A HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servo controller, a memory, and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus.
FIG. 1
illustrates a well known disk/head assembly
12
and a preamplifier
14
. The preamplifier
14
handles both read functions and write functions. Not illustrated in
FIG. 1
, for clarity, is the Magneto-resistive (MR) head that connects to the preamplifier
14
. An MR head works through magnetic media, using a different portion of the head to perform either a read or a write function. The write function portion of the MR head is inductive while the read function portion of the head acts as a magneto-resistive element to sense magnetic shifts in the disk assembly
12
.
FIG. 2
is a simplified schematic diagram illustrating a well known portion of a read channel circuit suitable for use with the preamplifier
14
shown in FIG.
1
.
Resistors R
MR1
-R
MR6
represent the resistive portion of six MR heads. An input amplification stage
18
of preamplifier
14
connects to the resistive portion, R
MR1
-R
MR6
of the MR heads. Later gain stages
20
of preamplifier
14
are connected to the outputs of input amplification stage
18
at nodes N
A
and M
B
. The read path outputs flow from the later gain stages
20
. The read channel inputs flow into preamplifier
14
from a head select logic stage. Preamplifier
14
may have as many as one to more than eight channels in typical HDD devices. Transistor SW
1
represents the read channel input enabling MOS transistor for head one of the six heads illustrated in FIG.
2
. The other enabling MOS transistors for heads two through six are not illustrated to preserve clarity. Head one is illustrated as the selected head, while the remaining five heads are illustrated in the off condition with the respective bases of input NPN transistors Q
2
-Q
6
being connected to the integrated circuit ground.
The architecture of input amplification stage
18
of preamplifier
14
can be seen to be formulated as a single ended amplifier having a single transistor Q
11
to set the voltage level on the load side of later gain stage
20
. A differential amplifier, as is known to one of ordinary skill in the art of amplifier design, uses two transistors to establish the voltages on nodes N and M. A bias current I
B
travels through the load resistor R
L
and through the collector of transistor Q
11
to set the voltage level on node M. A bias current I
B/&agr;
passes through a scaling resistor
20
RL
to set a reference voltage level on node N. The read head is generally biased at about 0.2 to about 0.5 volts to improve linearity characteristics during a read operation. This read head bias voltage is established via a feedback loop created by transconductance amplifier
22
across nodes M and N such that the amplifier
22
output is connected to the base of transistor Q
1
through MOS switch SW
1
. This structure creates a pseudo-balanced output on the reader load resistors R
L
and
20
RL
such as would exist if a differential amplifier were used in the input amplification stage.
Operation of Prior Art Preamplifier
14
NPN bipolar transistors Q
11
and Q
1
are active when head one is selected. Together with the load resistor R
L
, Q
11
and Q
1
form a cascade amplifier. A cascade amplifier is a high bandwidth amplifier suitable for processing data at high speeds on the order of Mbits/sec. Both Q
11
and Q
1
are configured as common base amplifiers. As a magneto-resistive (MR) head moves over data, the head resistance R
MRX
varies much like an alternating current signal in series with the head resistance R
MRX
. The NPN bipolar transistors Q
11
and Q
1
amplify a signal proportional to this variation in head resistance R
MRX
. This amplified ac signal is passed through the load resistor R
L
and into the base of emitter follower transistor Q
8
. The amplified ac signal then passes on to node M
B
that forms one input of the later gain stage
20
that is configured as a differential amplifier. The second input of the amplifier
20
is node N
A
that is set to be at a dc bias voltage equal to the voltage on the node M
B
. Ideally, the node N
A
should not have an alternating current signal passing through it. Thus, the reference side of the single ended input amplification stage
18
consists of transistors Q
B
, Q
21
and the scaling resistor
20
RL
. This structure supplies a current I
B/&agr;
through the scaling resistor
20
RL
, that provides a reference voltage at node N. Those skilled in the art will readily appreciate that if the dc voltage on nodes M and N are the same, then the input voltage on differential amplifier
20
at nodes N
A
and M
B
are the same. Thus, only node M
B
will see an ac signal. Because the dc voltages are equal in magnitude, the differential amplifier
20
will amplify only the ac signal and send it onto later gain stages.
FIGS. 3A and 3B
show a more detailed schematic diagram illustrating a known architecture for a HDD read circuit MR head preamplifier
100
having a bipolar transistor differential amplifier structure and that is generally used for processing digital data at speeds up to about 1.6 Mbits/sec. These figures shall be used herein after to more particularly describe limitations associated with presently known preamplifier architectures. Looking now at
FIG. 3A
, the resistors R
RM1-R
MX
represent the variable head resistance associated with each respective magneto-resistive (MR) head. The following operating principles, although described with reference to resistor R
RM1
, apply equally to each MR head. A read signal generated via R
RM1
is first amplified by a cascade amplifier formed by transistors Q
12
and Q
110
as well as load resistor R
L
depicted in stage
1
of FIG.
3
A. The amplified read signal thus appears across load resistor R
L
. The signal across load resistor R
L
is applied to an emitter follower amplifier formed by bipolar transistor Q
16
, also shown in stage
1
. Following amplification of the read signal via transistor Q
16
, the amplified read signal is then passed to a differential amplifier comprising bipolar transistors Q
21
, Q
22
, Q
23
and Q
24
illustrated in stage
2
. Although further amplification and signal processing takes place in stage
3
of the MR head preamplifier
100
, this amplification and signal processing is not relevant to the present discussion. Therefore, discussion of the

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