Low-noise magneto-resistive amplifier using CMOS technology

Details Low-noise magneto-resistive amplifier using CMOS technology Low-noise magneto-resistive amplifier using CMOS technology

1998-01-29

2001-04-17

Kim, W. Chris (Department: 2652)

Dynamic magnetic information storage or retrieval

General recording or reproducing

Specifics of the amplifier

C360S046000, C360S061000

Reexamination Certificate

active

06219195

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic amplifiers, particularly to low-noise amplifier circuits implemented using complementary metal oxide semiconductor (CMOS) technology for magneto-resistive (MR) applications.
BACKGROUND OF THE INVENTION
In conventional disk drive electronics, magnetic head circuitry is provided for amplifying signals read using magnetic heads, particularly so-called Magneto-Resistive (MR) heads. However, a common problem occurring during MR head operation is voltage discharge to MR heads arising when the head touches disc media.
Hence, due to sensitivity to possible damage from discharge, known designs for MR amplifiers do not operate using conventional five volt power supply. (See U.S. Pat. Nos. 4,786,993 and 5,327,303). In fact, to reduce such damage, conventional MR amplifier designs require either dual power supply voltages with grounded disk assembly or disk assemblies which float at potential equal to that of MR head. (See U.S. Pat. No. 4,879,610 to Jove et al. wherein negative power supply added to amplifier thereby raising total voltage of circuit over five volts, and rotating disk assembly biased from circuit ground to equalize potential of rotating discs with that of MR head. Additionally, U.S. Pat. No. 5,444,579 to Klein et al., discloses MR amplifier design with one end of MR head grounded, but amplifier bias current cannot be optimized for noise performance since MR head and input transistor share current.)
Furthermore, to operate properly, MR heads are typically DC biased. However, unless such DC bias is removed before read signal is received by amplifier, the amplifier may saturate. Commonly coupling capacitors are used to remove DC component from AC signal. However, value of DC blocking coupling capacitor tend to be relatively large and inappropriate for chip integration, particularly when multiple heads require many such capacitors. (See U.S. Pat. No. 4,833,559 to Belk which multiplexes MR elements into external capacitor, and multiplexing transistors are relatively large, thereby introducing substantial amplifier noise.)
There is a need, therefore, for improved, integrated design for low-noise, magneto-resistive pre-amplifier circuits, particularly for implementation in CMOS technology.
SUMMARY OF THE INVENTION
The invention resides in an integrated MOS circuit for amplifying a DC-biased signal received from a magneto-resistive (MR) head, which is grounded at one end. The amplifier circuit includes a blocking capacitor for decoupling current in the MR head from flowing into the amplifier circuit. A low-noise amplifier (LNA) circuit pre-amplifies the received signal, and a programmable high-pass filter (HPF) filters the amplified signal and generates therefrom a differential output signal.
Preferably, the MR head is biased at an optimal point by a current source to generate the received input signal. Such current source is powered by a regulator to reduce noise contribution from Vcc due to finite output impedance of current source. The LNA is a self-biased CMOS circuit which minimizes input-referred noised, without using negative power supply. A relatively small MOS transistor with feedback tracking loop replaces self-bias resistor, which can be chosen selectably as determination factor of lower corner cut-off frequency. This facilitates use of relatively large-value resistor, thereby enabling on-chip integration of the DC blocking input capacitor. As configured, Gm—Gm amplifier circuitry increases gain bandwidth product and minimizes parasitic effects of MOS transistors.
Additionally, the HPF circuit is programmable by adjusting a cut-off frequency, and includes a multiplexer for selecting an amplified signal from various MR heads. The selected signal is coupled to a differential input transistor and resistor-capacitor (RC) network, which is coupled to a differential input transistor. A differential output buffer, coupled to the HPF, generates from the filtered signal differential output signals and functions as a single-ended input to differential output converter. Furthermore, a thermal asperity correction circuit responds to a signal which indicates a thermal asperity event, whereby the correction circuit causes speed-up correction according to programmable HPF settings.


REFERENCES:
patent: 4786993 (1988-11-01), Jove et al.
patent: 4833559 (1989-05-01), Belk
patent: 4879610 (1989-11-01), Jove et al.
patent: 5327303 (1994-07-01), Smith
patent: 5331478 (1994-07-01), Aranovsky
patent: 5444579 (1995-08-01), Klein et al.
patent: 5455816 (1995-10-01), Bitting
patent: 5548453 (1996-08-01), Sasaki et al.
patent: 5559646 (1996-09-01), Voorman et al.
patent: 5625320 (1997-04-01), Hagerty
patent: 5841603 (1998-11-01), Ramalho et al.
patent: 5898532 (1999-04-01), Du et al.
patent: 6038090 (2000-03-01), Freitas

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