Low noise low distortion class D amplifier

Details Low noise low distortion class D amplifier Low noise low distortion class D amplifier

1999-11-10

2001-05-15

Pascal, Robert (Department: 2817)

Amplifiers

Modulator-demodulator-type amplifier

C330S20700P

Reexamination Certificate

active

06232833

ABSTRACT:

This invention provides circuits and techniques that reduce distortion caused by jitter and asymmetry in turn on delay (dead time) in class D audio amplifiers. The circuits described here minimize noise and ensure that turn on delays for both MOSFETs in the bridge are matched. This matching minimizes distortion. By minimizing jitter this circuit also improves the signal-to-noise ratio (SNR) and the dynamic range of class D amplifiers.
BACKGROUND
Class D amplifiers typically have a very high noise floor. Their noise is caused by jitter in the output of the pulse width modulator (PWM) comparator and by jitter associated with the duration of the turn on delay. In a class D amplifier, turn on delay is time that is intentionally added to half bridge circuits to prevent simultaneous conduction in the FETs. Most designers skilled in the art are aware of the first source of noise. As a result, they only use ultra low noise comparators to generate the PWM signal. The second source of jitter is often overlooked, but is just as important. Almost all dead time circuits are implemented with a fixed turn on delay. This allows the FET that is turning off to turn off before the other FET turns on. Dead time has long been recognized as the predominant form of distortion in class D amplifiers. Dead time creates odd order harmonics, and asymmetry in the dead time for the lower and upper FETs creates second order distortion. The circuit described here ensures that this source of distortion is minimized.
SUMMARY
The invention achieves lower distortion by using the same timing capacitor and resistor to set each turn on delay. This minimizes distortion by ensuring that there is no asymmetry in the turn on delays for the FETs. Since turn on delay jitter is an important source of noise, this circuit also implements techniques to minimize jitter. The result is a class D amplifier with 120 db of dynamic range and a SNR greater than 115 db (less than 100 &mgr;v of residual noise).
The invention works with any analog PWM modulation technique, fixed or variable frequency. Since all bridge topologies require some dead time, this circuit can be used in a wide variety of applications. An ultra low noise comparator generates the PWM signal. The low jitter dead time circuit (LJTC) then generates a turn on delay to prevent shoot through. These delayed logic signals drive the output MOSFETs through level shifters and gate drivers. The bridge circuit is connected between high and low voltage power busses and has at least two MOSFETs connected in series with each other.
A pair of first and second shunt regulators regulate current supplied to the LJDT circuit
50
. Shunt regulators are preferred over series regulators because shunt regulation removes high frequency ripple much better than series regulation. Since turn on delays are typically around 100-200 ns, only high frequency ripple on the supplies will contribute to jitter. A resistor and capacitor set timing for the dead time circuitry. At each PWM transition, the capacitor charges until it reaches a pre-determined threshold. An ultra low noise comparator detects threshold crossing. A pair of latches allows one to use the same resistor and capacitor to set the turn on delay for both the upper and lower FETS. This ensures that the turn on delay times for each FET match very well, and thus minimizes the distortion that is introduced by this delay. Timing RC filter results in low jitter because the resistor is connected to a shunt regulated supply and the cathode of the capacitor is connected to the ground plane. High frequency ripple on the supplies is minimized by shunt regulation and the RC filter further filters any ripple present. The result is a jitter free turn on delay resulting in a class D amplifier with a very low noise floor.


REFERENCES:
patent: 4554512 (1985-11-01), Aiello
patent: 5805020 (1998-09-01), Danz et al.
patent: 5973569 (1999-10-01), Nguyen
patent: 6118336 (2000-09-01), Pullen et al.

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