Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1998-12-24
2001-02-20
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S532000, C327S552000
Reexamination Certificate
active
06191647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device reducing a noise on LSI power supply nets followed by a high speed operation. More specifically, the present invention relates to a low noise integrated circuit device including a semiconductor (e.g., CMOS), in which a power supply current flows during only a specified period of time.
2. Description of the Related Art
Followed by a high speed operation and a high integration of a semiconductor integrated circuit, a power supply current required by the integrated circuit device, particularly, simultaneous switching current, has been increasing. There is a problem that a noise occurs on LSI power supply nets, caused by resistance and inductance of power supply wiring that has to be fine to supply an electric power to the integrated circuit. Generally, a bypass condenser is used to reduce the noise on LSI power supply nets.
FIG. 11
shows a noise reducing method using the bypass condenser on LSI power supply nets. An integrated circuit
110
is connected to a power supply VDD at a connection point N
5
and connected to a power supply VSS at a connection point N
6
. An impedance
111
exists in a wiring between the power supply VDD and the connection point N
5
. An impedance of a wiring between the power supply VSS and the connection point N
6
can be ignored because of its small value. When the integrated circuit
100
includes a logic integrated circuit with a plurality of gates that perform a simultaneous turn-on and off, a power supply current of the integrated circuit
110
has quick rise-up and down characteristics and for instance, becomes a pulse current flowing in synchronism with a clock signal. At this time, a noise L di/dt occurs dues to an inductance component of the impedance
111
. Accordingly, to reduce the noise on LSI power supply nets, the power supply current is bypassed by connecting a condenser
112
between the connection points N
5
and N
6
. Prior art relating to this kind of bypass condenser is described, for instance, in page 1166 to 1177 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 5 OCTOBER 1990.
SUMMARY OF THE INVENTION
A capacity of a bypass condenser mounted for the integrated circuit is limited in a highly integrated circuit device. While the bypass condenser discharges accumulated electric charges and supplies the electric charges to the integrated circuit, the discharge is followed by a voltage drop. When a capacity of the condenser
112
is C and an amount of electric charges of supply is Q in
FIG. 11
, a bypass of the power supply current is followed by a voltage drop of &Dgr;N=Q/C. In other words, if a capacity of the bypass condenser becomes short because of the limit of mounting density in the integrated circuit device and electric charges supplied from a power supply becomes short due to an influence of resistance and inductance, a power supply voltage supplied to the integrated circuit drops. Thus, if an amount of a noise on LSI power supply nets is &Dgr;V, the bypass condenser can only supply an amount of electric charges of Q=C&Dgr;V to the integrated circuit. Therefore, there is a problem that a bypass condenser having a huge area is required to reduce a noise on LSI power supply nets because a part of the total amount of electric charges CV stored in the bypass condenser can only be supplied to the integrated circuit.
There is another problem following a high speed operation of an integrated circuit.
FIG. 12
shows an example of noise on LSI power supply nets occurring in a semiconductor chip. Assuming that a noise on LSI power supply nets an &Dgr;VA occurs in an area A on the chip, an amplitude of the noise on LSI power supply nets becomes &Dgr;VB (&Dgr;VA>>&Dgr;VB) in an area B isolated from the area A because the noise on LSI power supply nets diminishes promptly over a distance with respect to a switching time of the integrated circuit being fast. Assuming that a bypass condenser (having a capacity of C) to reduce a noise on LSI power supply nets occurring in the area A is placed in the area B, the bypass condenser can only supply electric charges of C&Dgr;VB to the integrated circuit and there is no time to reduce a noise on LSI power supply nets occurring in the area A for the purpose of propagation delay from the area B to the area A. In other words, it is required to place the bypass condenser in the vicinity of a source of the noise.
However, there is a problem that the bypass condenser is required to be placed onto the whole area of the chip and that causes an increase of the chip area since a source generating the noise is distributed into a whole area of the chip in an actual integrated circuit.
An object of the present invention is therefore to provide a low noise integrated circuit device reducing a noise on LSI power supply nets and further concretely, further objects are the following (1) to (11).
(1) Reducing the noise on LSI power supply nets occurring in an arbitrary place including a location in a semiconductor chip.
(2) Predicting an occurrence of the noise on LSI power supply nets and reducing it.
(3) Regulating an amount of electric charges supplied to the integrated circuit by the respective noise reducing means for reducing a noise occurring locally.
(4) Supplying a required and/or enough amount of electric charges for reducing the noise on LSI power supply nets to the integrated circuit, even if a capacity of a condenser is small.
(5) Supplying a required and/or an enough amount of electric charges for reducing the noise on LSI power supply nets to the integrated circuit, even if a capacity of a condenser is small and a power supply voltage supplied to the integrated circuit device has one kind.
(6) Supplying a required and/or an enough amount of electric charges for reducing the noise on LSI power supply nets to a positive and negative power supply of the integrated circuit, even if a capacity of a condenser is small.
(7) Preparing a condenser able to charge with a higher voltage than a positive power supply voltage of the integrated circuit.
(8) Preparing a noise reducing means having the least leakage current.
(9) Preparing a noise reducing means on LSI power supply nets having means for determining an amount of electric charges supplied to the integrated circuit.
(10) Preparing means able to measure a noise voltage on LSI power supply nets occurred in the positive power supply of the integrated circuit.
(11) Preparing a noise measuring means having a high precision on LSI power supply nets.
REFERENCES:
patent: 5972553 (1999-10-01), Kim
H. Schettler et al, “A CMOS Mainframe Processor with 0.5um Channel Length”, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1166-1177.
Iwanaga Tomohisa
Kato Takeshi
Saito Tatsuya
Tanaka Katsuya
Uemura Tetsuya
Hitachi , Ltd.
Le Dinh T.
Mattingly Stanger & Malur, P.C.
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