Low-noise, high-linearity analog multiplier

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

Reexamination Certificate

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Reexamination Certificate

active

07088169

ABSTRACT:
An analog multiplier for multiplying a first analog voltage signal at a first frequency by a second analog voltage signal at a second frequency, comprising a first stage for converting the first analog voltage signal into a first and a second current signals, and a second stage comprising a first and a second cross-coupled current-switching pairs, driven by the second voltage signal, the first and second current-switching pairs having respective current inputs for receiving the first and the second current signals, respectively. Parasitic capacitances are inherently associated with each current input of the current-switching pairs. A compensation circuit is coupled to the current inputs of the current-switching pairs for compensating the parasitic capacitances.

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Manstretta D et al; “A 3.18/spl mu/m CMOS directi conversion receive front-end for UMTS”.
ISSCC 2002/ Session 14 / Cellular RF Wireless / 14.6 vol. 1, 2002, pp. 240-463, XP010585550.

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