Low noise-high gain JFET amplifier for a piezoelectric transduce

Amplifiers – With semiconductor amplifying device – Including field effect transistor

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330297, 330300, H03F 3185

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active

042142156

ABSTRACT:
A low-noise junction field effect depletion mode transistor amplifier and a signal retrieval network therefor is described. The junction (JFET) is used to amplify the signal from a piezoelectric transducer which forms the sensing element of a bone conduction microphone. A conventional transistor or Darlington pair is provided with a base electrode coupled to the source electrode of the JFET and a collector electrode coupled to the JFET drain electrode. The emitter circuit of the transistor includes a first voltage divider for feeding back a portion of the emitter signal to the base circuit of the transistor and another portion to the gate circuit of the JFET through the piezoelectric transducer. A second voltage divider is provided in the feedback path from the first divider to the transistor base to apply a portion of the base feedback signal to the JFET gate through the gate input resistor. By suitably selecting a high enough bias voltage for the JFET and by provision of the output transistor and associated feedback, the amplified output signal can be taken from either of the D.C. bias supply lines, namely, the positive line from the drain electrode of the JFET or the negative supply line at the bottom of the first voltage divider. Further solid state circuit means are provided for retrieving the amplified output signal from either of said supply lines with maximum gain and signal output.

REFERENCES:
patent: 3436672 (1969-04-01), Delagrange
patent: 3462701 (1969-08-01), Miller
patent: 3501711 (1970-03-01), Moran
patent: 4009447 (1977-02-01), Wolf et al.
patent: 4092701 (1978-05-01), Bumgardner
Towers, "High Input-Impedance Amplifier Circuits", Wireless World, Jul. 1968, pp. 197-201.
"Product Survey: Field-Effect Transistors", Electronic Design, Apr. 26, 1963, pp. 66-69.

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