Low-noise frequency divider

Details Low-noise frequency divider Low-noise frequency divider

1998-04-14

2000-12-19

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327115, H03K 2100

Patent

active

061631825

ABSTRACT:
A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.

REFERENCES:
patent: 5020082 (1991-05-01), Takeda
patent: 5172400 (1992-12-01), Maemura
patent: 5524037 (1996-06-01), Donig et al.
"Frequency Dividers For Ultra-High Frequencies" by W.D. Kasperkovitz, Philips Technical Review 38, 1978/79, No. 2, pp. 54-68.
"PLL-Synthesizerschaltkreis U 1056 D", by K.D. Moller, Radio Fernsehen Elektronik, vol. 39, No. 4, 1990, pp. 230, 261-263.

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