Low-noise, fast-lock phase-lock loop with...

Details Low-noise, fast-lock phase-lock loop with... Low-noise, fast-lock phase-lock loop with...

2001-06-26

2003-01-07

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

C331S016000, C331S017000

Reexamination Certificate

active

06504437

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to phase-lock loops and specifically a fast locking phase-lock loop having fine output resolution, low jitter noise and “gearshift” control.
BACKGROUND
A phase-lock loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. Phase locked loop (PLL) designers often have a major challenge with regard to the simultaneous achievement of fine output resolution (narrow channel spacing), fast lock time, and low jitter. This can be particularly difficult because the low loop bandwidth needed to reduce jitter and improve loop stability phase margin increases PLL locking time.
Typically, in PLL circuits, the frequency of the input signal differs from the desired frequency of the PLL output signal. Thus, frequency division circuitry is implemented in PLL circuits to compensate for this difference. Two types of commonly implemented division circuits are integer-N and fractional-N divider circuits. In an integer-N divider, a denominator N is variable in integer steps. The smallest step change in the frequency of the output signal provided by an integer-N PLL (comprising an integer-N divider circuit) is equal to the frequency of the signal provided to the input of the PLL. Thus, output signal resolution of a PLL circuit is limited to the frequency of the PLL input signal. In order to produce smaller step changes in the output frequency, circuits known as fractional-N divider circuits have been devised. Fractional-N divider circuits typically switch the divide ratio of the divider between two different values on successive comparison cycles of the phase detector to obtain an average denominator value between the two values. It is well known in the art that by dividing by a value, n, sometimes and n+1 at other times, the average denominator value is N, where n<N<n+1. For example, a divide ratio of 200.5 can be achieved by alternately switching the denominator between 200 and 201. Fraction-N PLL circuitry is described in a paper titled, “Delta-Sigma Modulation In Fraction −N Frequency Synthesis,” authored by T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, published in the IEEE Journal of Solid State Circuits, volume 28, no. 5, May 1993, pages 553-559, which is incorporated by reference herein, in its entirety.
Fractional-N PLLs provide relatively fast lock times. However, as the denominator (divider) switches between different division ratios, unwanted sidebands are introduced in the output spectrum of the frequency of the PLL output signal. These unwanted sidebands are referred to a phase noise or jitter. To avoid degradation of the PLL circuit performance due to jitter, a more complex loop filter having a narrow bandwidth may be implemented. However, a more complex loop filter contributes to slower lock times. This can result in less than optimal tracking or signal lock. Thus, a need exists for a PLL circuit and a technique for controlling a PLL circuit, which provide the loop stability and low jitter associated with an integer-N PLL and also provide the fine output resolution and fast lock times associated fractional-N PLL.
SUMMARY OF THE INVENTION
A method for controlling a phase-lock loop (PLL) circuit includes configuring the PLL circuit in two configurations. The first configuration provides a relatively fast lock time compared to lock times provided by the second configuration. The second configuration provides more stability than the first configuration.
In another embodiment of the invention, a phase-lock loop (PLL) circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). The phase/frequency detector compares the phase of a feedback signal and an input signal, and provides an error signal in accordance with the difference. The charge pump receives the error signal and provides a charge signal. The loop filter receives the charge signal and providing a loop filter signal. The bandwidth of the loop filter is increased during a first phase of operation decreased during a second phase of operation.


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F. Gardner,Phaselock Techniques, 1979, p. 89.
T. Riley, M. Copeland and T. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,”IEEE Journal of Solid-State Circuits, May 1993, pp. 553-559.
L. Sun, T. Lepley, F. Nozahic, A. Bellissant, T. Kwasniewski and B. Heim, “Reduced Complexity, High Performance Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis,”IEEE Journal of Solid-State Circuits, 1999, pp. II-152-II-155.

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